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Today's high level synthesis tools: a comparison

Wim Meeus UGent and Dirk Stroobandt UGent (2010) STW.ICT conference, Abstracts.
abstract
High-level synthesis (HLS) tools greatly reduce the effort required in Register Transfer Level (RTL) design by automatically converting behavioral algorithms into synthesizable hardware descriptions. These tools are being actively developed, and even though they have been around for more than 10 years, they have only recently been adopted by industry. As a result of the reduced designer effort, advantages of high level synthesis include an improved time to market and the possibility to do extensive design space exploration. In this work, we present a comparison of some of today's tools based on our own experience of implementing an image processing algorithm. Different features are highlighted, such as design entry, capabilities, synthesis results, verification options and the learning curve for the designer. We have found that the high-level synthesis tools greatly differ in their features and also in the types of applications they can handle. Because of design space exploration capabilities, the quality of HLS generated hardware is comparable to manual RTL design, in terms of area, latency and also power consumption. Among the tools that we have evaluated so far, the most impressive results were obtained using Catapult C from Mentor Graphics.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
keyword
Behavioral synthesis, Electronic design automation, High level synthesis, Electronic system level
in
STW.ICT conference, Abstracts
conference name
STW.ICT Conference (PRORISC - 2010)
conference location
Veldhoven, The Netherlands
conference start
2010-11-18
conference end
2010-11-19
language
English
UGent publication?
yes
classification
C3
copyright statement
I have retained and own the full copyright for this publication
id
1339511
handle
http://hdl.handle.net/1854/LU-1339511
date created
2011-06-24 10:54:23
date last changed
2016-12-19 15:35:21
@inproceedings{1339511,
  abstract     = {High-level synthesis (HLS) tools greatly reduce the effort required in Register Transfer Level (RTL) design by automatically converting behavioral algorithms into synthesizable hardware descriptions. These tools are being actively developed, and even though they have been around for more than 10 years, they have only recently been adopted by industry. As a result of the reduced designer effort, advantages of high level synthesis include an improved time to market and the possibility to do extensive design space exploration. In this work, we present a comparison of some of today's tools based on our own experience of implementing an image processing algorithm. Different features are highlighted, such as design entry, capabilities, synthesis results, verification options and the learning curve for the designer. We have found that the high-level synthesis tools greatly differ in their features and also in the types of applications they can handle. Because of design space exploration capabilities, the quality of HLS generated hardware is comparable to manual RTL design, in terms of area, latency and also power consumption. Among the tools that we have evaluated so far, the most impressive results were obtained using Catapult C from Mentor Graphics.},
  author       = {Meeus, Wim and Stroobandt, Dirk},
  booktitle    = {STW.ICT conference, Abstracts},
  keyword      = {Behavioral synthesis,Electronic design automation,High level synthesis,Electronic system level},
  language     = {eng},
  location     = {Veldhoven, The Netherlands},
  title        = {Today's high level synthesis tools: a comparison},
  year         = {2010},
}

Chicago
Meeus, Wim, and Dirk Stroobandt. 2010. “Today’s High Level Synthesis Tools: a Comparison.” In STW.ICT Conference, Abstracts.
APA
Meeus, Wim, & Stroobandt, D. (2010). Today’s high level synthesis tools: a comparison. STW.ICT conference, Abstracts. Presented at the STW.ICT Conference (PRORISC - 2010).
Vancouver
1.
Meeus W, Stroobandt D. Today’s high level synthesis tools: a comparison. STW.ICT conference, Abstracts. 2010.
MLA
Meeus, Wim, and Dirk Stroobandt. “Today’s High Level Synthesis Tools: a Comparison.” STW.ICT Conference, Abstracts. 2010. Print.