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A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks.

Henk Neefs, Hans Vandierendonck UGent and Koen De Bosschere UGent (2000) Proceedings of the 6th International Symposium on High-Performance Computer Architecture, IEEE Computer Society, Toulouse, Frankrijk, 2000. p.313-324
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
in
Proceedings of the 6th International Symposium on High-Performance Computer Architecture, IEEE Computer Society, Toulouse, Frankrijk, 2000
pages
313-324 pages
language
English
UGent publication?
yes
classification
C1
id
129754
handle
http://hdl.handle.net/1854/LU-129754
date created
2004-01-14 13:36:00
date last changed
2016-12-19 15:35:22
@inproceedings{129754,
  author       = {Neefs, Henk and Vandierendonck, Hans and De Bosschere, Koen},
  booktitle    = {Proceedings of the 6th International Symposium on High-Performance Computer Architecture, IEEE Computer Society, Toulouse, Frankrijk, 2000},
  language     = {eng},
  pages        = {313--324},
  title        = {A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks.},
  year         = {2000},
}

Chicago
Neefs, Henk, Hans Vandierendonck, and Koen De Bosschere. 2000. “A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks.” In Proceedings of the 6th International Symposium on High-Performance Computer Architecture, IEEE Computer Society, Toulouse, Frankrijk, 2000, 313–324.
APA
Neefs, H., Vandierendonck, H., & De Bosschere, K. (2000). A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks. Proceedings of the 6th International Symposium on High-Performance Computer Architecture, IEEE Computer Society, Toulouse, Frankrijk, 2000 (pp. 313–324).
Vancouver
1.
Neefs H, Vandierendonck H, De Bosschere K. A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks. Proceedings of the 6th International Symposium on High-Performance Computer Architecture, IEEE Computer Society, Toulouse, Frankrijk, 2000. 2000. p. 313–24.
MLA
Neefs, Henk, Hans Vandierendonck, and Koen De Bosschere. “A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks.” Proceedings of the 6th International Symposium on High-Performance Computer Architecture, IEEE Computer Society, Toulouse, Frankrijk, 2000. 2000. 313–324. Print.