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Control for power gating of wires

Kris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert UGent and Wilfried Philips UGent (2010) IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 18(9). p.1287-1300
abstract
In the deep sub-micron domain wires consume more power than transistors. Power Gating for Wires is a form of bus segmentation that alleviates the power loss from on-chip interconnects, by switching off the supply voltage from inactive drivers, cycle by instruction-cycle. The success of Power Gating for Wires depends much on control: the gain from segmentation can conceivably be undone by control costs. Yet during design exploration, the data required for statistical analysis are not available. A theory of efficient control for Power Gating for Wires and a design framework, determining the balance of cost factors, at an early stage, are both needed. In this paper, we formulate a theory of Useful State Analysis to obtain minimal-redundancy encoding of control information. We establish two figures of merit, based on network topology: Intrinsic Sectioning Gain and Useful Encoding Efficiency. They quantify the power loss reduction achievable, and the success of Useful State Analysis in keeping control costs low. We propose a design pattern for the operation of a control plane, wherein the costs of control can be identified. From use cases, we find that architectures can have an Intrinsic Sectioning Gain of 50% and more. Useful Encoding Efficiency is found to be in a range of 44-80% for some common multipath architectures. Although ultimately, the limits of feasibility to control Power Gating for Wires must be decided by means of statistical analysis, we find Useful State Analysis is applicable to networks with tens of terminals, and that our method of control scales well with increasing network size and complexity.
Please use this url to cite or link to this publication:
author
organization
year
type
journalArticle (original)
publication status
published
subject
keyword
DESIGN, segmented bus, ARCHITECTURE, SYSTEMS, Control with minimum redundancy, program-controlled circuit switching, power-aware design, wire sectioning, useful state analysis, supply voltage gating
journal title
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
volume
18
issue
9
pages
1287 - 1300
Web of Science type
Article
Web of Science id
000281735900003
JCR category
ENGINEERING, ELECTRICAL & ELECTRONIC
JCR impact factor
0.904 (2010)
JCR rank
134/247 (2010)
JCR quartile
3 (2010)
ISSN
1063-8210
DOI
10.1109/TVLSI.2009.2022269
language
English
UGent publication?
yes
classification
A1
copyright statement
I have transferred the copyright for this publication to the publisher
id
1242422
handle
http://hdl.handle.net/1854/LU-1242422
date created
2011-05-25 15:26:00
date last changed
2016-12-19 15:45:58
@article{1242422,
  abstract     = {In the deep sub-micron domain wires consume more power than transistors. Power Gating for Wires is a form of bus segmentation that alleviates the power loss from on-chip interconnects, by switching off the supply voltage from inactive drivers, cycle by instruction-cycle. The success of Power Gating for Wires depends much on control: the gain from segmentation can conceivably be undone by control costs. Yet during design exploration, the data required for statistical analysis are not available. A theory of efficient control for Power Gating for Wires and a design framework, determining the balance of cost factors, at an early stage, are both needed. In this paper, we formulate a theory of Useful State Analysis to obtain minimal-redundancy encoding of control information. We establish two figures of merit, based on network topology: Intrinsic Sectioning Gain and Useful Encoding Efficiency. They quantify the power loss reduction achievable, and the success of Useful State Analysis in keeping control costs low. We propose a design pattern for the operation of a control plane, wherein the costs of control can be identified. From use cases, we find that architectures can have an Intrinsic Sectioning Gain of 50\% and more. Useful Encoding Efficiency is found to be in a range of 44-80\% for some common multipath architectures. Although ultimately, the limits of feasibility to control Power Gating for Wires must be decided by means of statistical analysis, we find Useful State Analysis is applicable to networks with tens of terminals, and that our method of control scales well with increasing network size and complexity.},
  author       = {Heyrman, Kris and Papanikolaou, Antonis and Catthoor, Francky and Veelaert, Peter and Philips, Wilfried},
  issn         = {1063-8210},
  journal      = {IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS},
  keyword      = {DESIGN,segmented bus,ARCHITECTURE,SYSTEMS,Control with minimum redundancy,program-controlled circuit switching,power-aware design,wire sectioning,useful state analysis,supply voltage gating},
  language     = {eng},
  number       = {9},
  pages        = {1287--1300},
  title        = {Control for power gating of wires},
  url          = {http://dx.doi.org/10.1109/TVLSI.2009.2022269},
  volume       = {18},
  year         = {2010},
}

Chicago
Heyrman, Kris, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, and Wilfried Philips. 2010. “Control for Power Gating of Wires.” Ieee Transactions on Very Large Scale Integration (vlsi) Systems 18 (9): 1287–1300.
APA
Heyrman, K., Papanikolaou, A., Catthoor, F., Veelaert, P., & Philips, W. (2010). Control for power gating of wires. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 18(9), 1287–1300.
Vancouver
1.
Heyrman K, Papanikolaou A, Catthoor F, Veelaert P, Philips W. Control for power gating of wires. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2010;18(9):1287–300.
MLA
Heyrman, Kris, Antonis Papanikolaou, Francky Catthoor, et al. “Control for Power Gating of Wires.” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.9 (2010): 1287–1300. Print.