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Link-time optimization for power efficiency in a tagless instruction cache

Timothy Jones, Sandro Bartolini, Jonas Maebe UGent and Dominique Chanet UGent (2011) Proceedings of the CGO (International Symposium on Code Generation and Optimization). p.32-41
abstract
The instruction cache is a critical component in any microprocessor. It must have high performance to enable fetching of instructions on every cycle. However, current designs waste a large amount of energy on each access as tags and data banks from all cache ways are consulted in parallel to fetch the correct instructions as quickly as possible. Existing approaches to reduce this overhead remove unnecessary accesses to the data banks or to the ways that are not likely to hit. However, tag hunks still need to be checked. This paper considers a new hybrid hardware and linker-assisted approach to tagless instruction caching. Our novel cache architecture, supported by the compilation toolchain, removes the need for tag checks entirely for the majority of cache accesses. The linker places frequently-executed instructions in specific program regions that are then mapped into the cache without the need for tag checks. This requires minor hardware modifications, no ISA changes and works across cache configurations. Our approach keeps the software and hardware independent, resulting in both backward and forward compatibility. evaluation on a superscalar processor with and without SMI' support shows power savings of 66% within the instruction cache with no loss of performance. This translates to a 49% saving when considering the combined power of the instruction cache and translation lookaside buffer, which is involved in managing our tagless scheme.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
keyword
instruction cache, link-time optimization, tagless cache, scratchpad memory
in
Proceedings of the CGO (International Symposium on Code Generation and Optimization)
issue title
2011 9TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON CODE GENERATION AND OPTIMIZATION (CGO)
pages
32 - 41
publisher
IEEE
place of publication
Piscataway, NJ, USA
conference name
9th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO - 2011)
conference location
Chamonix, France
conference start
2011-04-02
conference end
2011-04-06
Web of Science type
Proceedings Paper
Web of Science id
000298560000006
ISSN
2164-2397
ISBN
9781612843551
DOI
10.1109/CGO.2011.5764672
project
HPC-UGent: the central High Performance Computing infrastructure of Ghent University
project
HiPEAC High-Performance Embedded Architecture and Compilation
language
English
UGent publication?
yes
classification
P1
copyright statement
I have transferred the copyright for this publication to the publisher
id
1205690
handle
http://hdl.handle.net/1854/LU-1205690
date created
2011-04-10 12:02:28
date last changed
2013-09-17 10:56:19
@inproceedings{1205690,
  abstract     = {The instruction cache is a critical component in any microprocessor. It must have high performance to enable fetching of instructions on every cycle. However, current designs waste a large amount of energy on each access as tags and data banks from all cache ways are consulted in parallel to fetch the correct instructions as quickly as possible. Existing approaches to reduce this overhead remove unnecessary accesses to the data banks or to the ways that are not likely to hit. However, tag hunks still need to be checked. This paper considers a new hybrid hardware and linker-assisted approach to tagless instruction caching. Our novel cache architecture, supported by the compilation toolchain, removes the need for tag checks entirely for the majority of cache accesses. The linker places frequently-executed instructions in specific program regions that are then mapped into the cache without the need for tag checks. This requires minor hardware modifications, no ISA changes and works across cache configurations. Our approach keeps the software and hardware independent, resulting in both backward and forward compatibility. evaluation on a superscalar processor with and without SMI' support shows power savings of 66\% within the instruction cache with no loss of performance. This translates to a 49\% saving when considering the combined power of the instruction cache and translation lookaside buffer, which is involved in managing our tagless scheme.},
  author       = {Jones, Timothy and Bartolini, Sandro and Maebe, Jonas and Chanet, Dominique},
  booktitle    = {Proceedings of the CGO (International Symposium on Code Generation and Optimization)},
  isbn         = {9781612843551},
  issn         = {2164-2397},
  keyword      = {instruction cache,link-time optimization,tagless cache,scratchpad memory},
  language     = {eng},
  location     = {Chamonix, France},
  pages        = {32--41},
  publisher    = {IEEE},
  title        = {Link-time optimization for power efficiency in a tagless instruction cache},
  url          = {http://dx.doi.org/10.1109/CGO.2011.5764672},
  year         = {2011},
}

Chicago
Jones, Timothy, Sandro Bartolini, Jonas Maebe, and Dominique Chanet. 2011. “Link-time Optimization for Power Efficiency in a Tagless Instruction Cache.” In Proceedings of the CGO (International Symposium on Code Generation and Optimization), 32–41. Piscataway, NJ, USA: IEEE.
APA
Jones, T., Bartolini, S., Maebe, J., & Chanet, D. (2011). Link-time optimization for power efficiency in a tagless instruction cache. Proceedings of the CGO (International Symposium on Code Generation and Optimization) (pp. 32–41). Presented at the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO - 2011), Piscataway, NJ, USA: IEEE.
Vancouver
1.
Jones T, Bartolini S, Maebe J, Chanet D. Link-time optimization for power efficiency in a tagless instruction cache. Proceedings of the CGO (International Symposium on Code Generation and Optimization). Piscataway, NJ, USA: IEEE; 2011. p. 32–41.
MLA
Jones, Timothy, Sandro Bartolini, Jonas Maebe, et al. “Link-time Optimization for Power Efficiency in a Tagless Instruction Cache.” Proceedings of the CGO (International Symposium on Code Generation and Optimization). Piscataway, NJ, USA: IEEE, 2011. 32–41. Print.