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A 5.8mW 72 dB ΣΔ-modulator ADC with 1.8MHz BW in 130nm CMOS

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Abstract
A double-sampling split ΣΔ-modulation ADC with bilinear integrators and a 7-level quantizer is presented. It achieves third order noise shaping with a second order modulator through quantization noise-coupling. The modulator is integrated in a 130nm CMOS technology. For a clock frequency of 36MHz and an oversampling ratio of 20 (1.8MHz signal bandwidth), it achieves 72 dB DR and 68 dB SNR. The prototype consumes 5.8mW from a 1.2V voltage supply.
Keywords
Analog-to-digital converters, 130nm CMOS technology, ΣΔ-modulation, noise-coupling, double sampling

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Chicago
De Bock, Maarten, and Pieter Rombouts. 2010. “A 5.8mW 72 dB ΣΔ-modulator ADC with 1.8MHz BW in 130nm CMOS.” In 13th IEEJ International Analog VLSI Workshop (AVLSIWS - 2010), Proceedings, 87–90. New York, NY, USA: IEEE.
APA
De Bock, Maarten, & Rombouts, P. (2010). A 5.8mW 72 dB ΣΔ-modulator ADC with 1.8MHz BW in 130nm CMOS. 13th IEEJ international analog VLSI workshop (AVLSIWS - 2010), Proceedings (pp. 87–90). Presented at the 13th IEEJ International Analog VLSI Workshop (AVLSIWS - 2010), New York, NY, USA: IEEE.
Vancouver
1.
De Bock M, Rombouts P. A 5.8mW 72 dB ΣΔ-modulator ADC with 1.8MHz BW in 130nm CMOS. 13th IEEJ international analog VLSI workshop (AVLSIWS - 2010), Proceedings. New York, NY, USA: IEEE; 2010. p. 87–90.
MLA
De Bock, Maarten, and Pieter Rombouts. “A 5.8mW 72 dB ΣΔ-modulator ADC with 1.8MHz BW in 130nm CMOS.” 13th IEEJ International Analog VLSI Workshop (AVLSIWS - 2010), Proceedings. New York, NY, USA: IEEE, 2010. 87–90. Print.
@inproceedings{1176812,
  abstract     = {A double-sampling split \ensuremath{\Sigma}\ensuremath{\Delta}-modulation ADC with bilinear integrators and a 7-level quantizer is presented. It achieves third order noise shaping with a second order modulator through quantization noise-coupling. The modulator is integrated in a 130nm CMOS technology. For a clock frequency of 36MHz and an oversampling ratio of 20 (1.8MHz signal bandwidth), it achieves 72 dB DR and 68 dB SNR. The prototype consumes 5.8mW from a 1.2V voltage supply.},
  author       = {De Bock, Maarten and Rombouts, Pieter},
  booktitle    = {13th IEEJ international analog VLSI workshop (AVLSIWS - 2010), Proceedings},
  keyword      = {Analog-to-digital converters,130nm CMOS technology,\ensuremath{\Sigma}\ensuremath{\Delta}-modulation,noise-coupling,double sampling},
  language     = {eng},
  location     = {Pavia, Italy},
  pages        = {87--90},
  publisher    = {IEEE},
  title        = {A 5.8mW 72 dB \ensuremath{\Sigma}\ensuremath{\Delta}-modulator ADC with 1.8MHz BW in 130nm CMOS},
  year         = {2010},
}