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Exploitable levels of ILP in future processors.

Henk Neefs, Koen De Bosschere UGent and Jan Van Campenhout UGent (1999) JOURNAL OF SYSTEMS ARCHITECTURE. 45(9). p.687-708
Please use this url to cite or link to this publication:
author
organization
year
type
journalArticle (original)
publication status
published
subject
journal title
JOURNAL OF SYSTEMS ARCHITECTURE
J. Syst. Architect.
volume
45
issue
9
pages
687-708 pages
Web of Science type
Article
Web of Science id
000079037400003
ISSN
1383-7621
language
English
UGent publication?
yes
classification
A1
id
117474
handle
http://hdl.handle.net/1854/LU-117474
date created
2004-01-14 13:35:00
date last changed
2016-12-19 15:37:24
@article{117474,
  author       = {Neefs, Henk and De Bosschere, Koen and Van Campenhout, Jan},
  issn         = {1383-7621},
  journal      = {JOURNAL OF SYSTEMS ARCHITECTURE},
  language     = {eng},
  number       = {9},
  pages        = {687--708},
  title        = {Exploitable levels of ILP in future processors.},
  volume       = {45},
  year         = {1999},
}

Chicago
Neefs, Henk, Koen De Bosschere, and Jan Van Campenhout. 1999. “Exploitable Levels of ILP in Future Processors.” Journal of Systems Architecture 45 (9): 687–708.
APA
Neefs, H., De Bosschere, K., & Van Campenhout, J. (1999). Exploitable levels of ILP in future processors. JOURNAL OF SYSTEMS ARCHITECTURE, 45(9), 687–708.
Vancouver
1.
Neefs H, De Bosschere K, Van Campenhout J. Exploitable levels of ILP in future processors. JOURNAL OF SYSTEMS ARCHITECTURE. 1999;45(9):687–708.
MLA
Neefs, Henk, Koen De Bosschere, and Jan Van Campenhout. “Exploitable Levels of ILP in Future Processors.” JOURNAL OF SYSTEMS ARCHITECTURE 45.9 (1999): 687–708. Print.