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Coarse-grained reconfigurable array architectures

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Abstract
Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.

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MLA
De Sutter, Bjorn, Praveen Raghavan, and Andy Lambrechts. “Coarse-grained Reconfigurable Array Architectures.” Handbook of Signal Processing Systems. Ed. Shuvra S Bhattacharyya et al. New York, NY, USA: Springer, 2010. 449–484. Print.
APA
De Sutter, B., Raghavan, P., & Lambrechts, A. (2010). Coarse-grained reconfigurable array architectures. In S. S. Bhattacharyya, E. F. Deprettere, R. Leupers, & J. Takala (Eds.), Handbook of signal processing systems (pp. 449–484). New York, NY, USA: Springer.
Chicago author-date
De Sutter, Bjorn, Praveen Raghavan, and Andy Lambrechts. 2010. “Coarse-grained Reconfigurable Array Architectures.” In Handbook of Signal Processing Systems, ed. Shuvra S Bhattacharyya, Ed F Deprettere, Rainer Leupers, and Jarmo Takala, 449–484. New York, NY, USA: Springer.
Chicago author-date (all authors)
De Sutter, Bjorn, Praveen Raghavan, and Andy Lambrechts. 2010. “Coarse-grained Reconfigurable Array Architectures.” In Handbook of Signal Processing Systems, ed. Shuvra S Bhattacharyya, Ed F Deprettere, Rainer Leupers, and Jarmo Takala, 449–484. New York, NY, USA: Springer.
Vancouver
1.
De Sutter B, Raghavan P, Lambrechts A. Coarse-grained reconfigurable array architectures. In: Bhattacharyya SS, Deprettere EF, Leupers R, Takala J, editors. Handbook of signal processing systems. New York, NY, USA: Springer; 2010. p. 449–84.
IEEE
[1]
B. De Sutter, P. Raghavan, and A. Lambrechts, “Coarse-grained reconfigurable array architectures,” in Handbook of signal processing systems, S. S. Bhattacharyya, E. F. Deprettere, R. Leupers, and J. Takala, Eds. New York, NY, USA: Springer, 2010, pp. 449–484.
@incollection{1153474,
  abstract     = {Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.},
  author       = {De Sutter, Bjorn and Raghavan, Praveen and Lambrechts, Andy},
  booktitle    = {Handbook of signal processing systems},
  editor       = {Bhattacharyya, Shuvra S and Deprettere, Ed F and Leupers, Rainer and Takala, Jarmo},
  isbn         = {9781441963444},
  language     = {eng},
  pages        = {449--484},
  publisher    = {Springer},
  title        = {Coarse-grained reconfigurable array architectures},
  url          = {http://dx.doi.org/10.1007/978-1-4419-6345-1_17},
  year         = {2010},
}

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