Advanced search
1 file | 1.78 MB

An efficient memory organization for high-ILP inner modem baseband SDR processors

Author
Organization
Abstract
his paper presents a memory organization for SDR inner modem baseband processors that focus on exploiting ILP. This memory organization uses power- efficient, single-ported, interleaved scratch-pad memory banks to provide enough bandwidth to a high-ILP processors. A system of queues in the memory interface is used to resolve bank conflicts among the single-ported banks, and to spread long bursts of conflicting accesses to the same bank over time. Bank address rotation is used to spread long bursts of conflicting accesses over multiple banks. All proposed techniques have been implemented in hardware, and are evaluated for a number of different wireless communication standards. For the 11a|n benchmarks, the overhead of stall cycles resulting from unresolved bank conflicts can be reduced to below 2% with the proposed organization. For 3GPP-LTE, the most demanding wireless standard we evaluated, the overhead is reduced to less than 0.13%. This is achieved with little energy and area overhead, and without any bank-aware compiler support.
Keywords
ACCESS, PARALLEL, MANAGEMENT, LOCALITY, SYSTEMS, SCHEME, DESIGN, VECTOR, Memory-level parallelism, Instruction-level parallelism, Software-defined radio, Memory queues, Interleaved memory

Downloads

  • (...).pdf
    • full text
    • |
    • UGent only
    • |
    • PDF
    • |
    • 1.78 MB

Citation

Please use this url to cite or link to this publication:

Chicago
De Sutter, Bjorn, Osman Allam, Praveen Raghavan, Roeland Vandebriel, Hans Capelle, Tom Vander Aa, and Bingfeng Mei. 2010. “An Efficient Memory Organization for high-ILP Inner Modem Baseband SDR Processors.” Journal of Signal Processing Systems for Signal Image and Video Technology 61 (2): 157–179.
APA
De Sutter, B., Allam, O., Raghavan, P., Vandebriel, R., Capelle, H., Vander Aa, T., & Mei, B. (2010). An efficient memory organization for high-ILP inner modem baseband SDR processors. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 61(2), 157–179.
Vancouver
1.
De Sutter B, Allam O, Raghavan P, Vandebriel R, Capelle H, Vander Aa T, et al. An efficient memory organization for high-ILP inner modem baseband SDR processors. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY. 2010;61(2):157–79.
MLA
De Sutter, Bjorn, Osman Allam, Praveen Raghavan, et al. “An Efficient Memory Organization for high-ILP Inner Modem Baseband SDR Processors.” JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 61.2 (2010): 157–179. Print.
@article{1153422,
  abstract     = {his paper presents a memory organization for SDR inner modem baseband processors that focus on exploiting ILP. This memory organization uses power- efficient, single-ported, interleaved scratch-pad memory banks to provide enough bandwidth to a high-ILP processors. A system of queues in the memory interface is used to resolve bank con\unmatched{fb02}icts among the single-ported banks, and to spread long bursts of con\unmatched{fb02}icting accesses to the same bank over time. Bank address rotation is used to spread long bursts of con\unmatched{fb02}icting accesses over multiple banks. All proposed techniques have been implemented in hardware, and are evaluated for a number of different wireless communication standards. For the 11a|n benchmarks, the overhead of stall cycles resulting from unresolved bank con\unmatched{fb02}icts can be reduced to below 2\% with the proposed organization. For 3GPP-LTE, the most demanding wireless standard we evaluated, the overhead is reduced to less than 0.13\%. This is achieved with little energy and area overhead, and without any bank-aware compiler support.},
  author       = {De Sutter, Bjorn and Allam, Osman and Raghavan, Praveen and Vandebriel, Roeland and Capelle, Hans and Vander Aa, Tom and Mei, Bingfeng},
  issn         = {1939-8018},
  journal      = {JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY},
  keyword      = {ACCESS,PARALLEL,MANAGEMENT,LOCALITY,SYSTEMS,SCHEME,DESIGN,VECTOR,Memory-level parallelism,Instruction-level parallelism,Software-defined radio,Memory queues,Interleaved memory},
  language     = {eng},
  number       = {2},
  pages        = {157--179},
  title        = {An efficient memory organization for high-ILP inner modem baseband SDR processors},
  url          = {http://dx.doi.org/10.1007/s11265-009-0412-x},
  volume       = {61},
  year         = {2010},
}

Altmetric
View in Altmetric
Web of Science
Times cited: