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Low-power 4-bit flash analogue to digital converter for ranging applications

Guy Torfs (UGent) , Zhisheng Li (UGent) , Johan Bauwelinck (UGent) , Xin Yin (UGent) , G Van der Plas and Jan Vandewege (UGent)
(2011) ELECTRONICS LETTERS. 47(1). p.20-21
Author
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Abstract
A 4-bit 700 MS/s flash ADC is presented in 0.18 mu m CMOS. By lowering the kickback noise of the individual comparators it was possible to reduce the power consumption to 4.43 mW. Improved calibration capabilities resulted in an INL and DNL smaller than 0.25 LSB. These low nonlinearities give rise to 3.77 effective number of bits at the Nyquist input frequency and this in turn yields an overall figure of merit of 0.46 pJ per conversion step, the lowest figure of merit reported for ADCs with sampling rate above 500 MHz in 0.18 mu m CMOS.
Keywords
ADC, CMOS, BAND

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Citation

Please use this url to cite or link to this publication:

Chicago
Torfs, Guy, Zhisheng Li, Johan Bauwelinck, Xin Yin, G Van der Plas, and Jan Vandewege. 2011. “Low-power 4-bit Flash Analogue to Digital Converter for Ranging Applications.” Electronics Letters 47 (1): 20–21.
APA
Torfs, G., Li, Z., Bauwelinck, J., Yin, X., Van der Plas, G., & Vandewege, J. (2011). Low-power 4-bit flash analogue to digital converter for ranging applications. ELECTRONICS LETTERS, 47(1), 20–21.
Vancouver
1.
Torfs G, Li Z, Bauwelinck J, Yin X, Van der Plas G, Vandewege J. Low-power 4-bit flash analogue to digital converter for ranging applications. ELECTRONICS LETTERS. 2011;47(1):20–1.
MLA
Torfs, Guy, Zhisheng Li, Johan Bauwelinck, et al. “Low-power 4-bit Flash Analogue to Digital Converter for Ranging Applications.” ELECTRONICS LETTERS 47.1 (2011): 20–21. Print.
@article{1143576,
  abstract     = {A 4-bit 700 MS/s flash ADC is presented in 0.18 mu m CMOS. By lowering the kickback noise of the individual comparators it was possible to reduce the power consumption to 4.43 mW. Improved calibration capabilities resulted in an INL and DNL smaller than 0.25 LSB. These low nonlinearities give rise to 3.77 effective number of bits at the Nyquist input frequency and this in turn yields an overall figure of merit of 0.46 pJ per conversion step, the lowest figure of merit reported for ADCs with sampling rate above 500 MHz in 0.18 mu m CMOS.},
  author       = {Torfs, Guy and Li, Zhisheng and Bauwelinck, Johan and Yin, Xin and Van der Plas, G and Vandewege, Jan},
  issn         = {0013-5194},
  journal      = {ELECTRONICS LETTERS},
  language     = {eng},
  number       = {1},
  pages        = {20--21},
  title        = {Low-power 4-bit flash analogue to digital converter for ranging applications},
  url          = {http://dx.doi.org/10.1049/el.2010.2213},
  volume       = {47},
  year         = {2011},
}

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