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A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms

Bertrand Rousseau, Philippe Manet, Igor Loiselle, Jean-Didier Legat and Hans Vandierendonck UGent (2010) 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP 2010). p.273-280
abstract
The power efficiency of an HMCP heavily depends on the architecture of its processor cores. It is thus very important to choose it carefully. When comparing processing architectures for their use in a many-core platform, one must evaluate its IPC, but also its power and area. Precise power and area evaluations can only be done with real implementations. However, comparing processor implementations is a difficult task since the implementation specifities introduce interferences on the performances. This paper proposes a methodology that allows to realize precise comparisons of performance for different processor architectures. Using this methodology, it is possible to choose the best architecture for an HMCP targeting DSP applications. The methodology is based on the use of a common architural template to build the cores, and on the application of specific optimizations when relevant. In order to validate the methodology, three RISC cores are implemented: a single-issue core, and two VLIW processors with respectively 3 and 5 issues. The implemented cores are precisely compared on a set of DSP kernels.
Please use this url to cite or link to this publication:
author
organization
year
type
conference (conferencePaper)
publication status
published
subject
keyword
processor architecture, homogeneous many-core, signal processing, power efficiency
in
2010 Conference on Design and Architectures for Signal and Image Processing (DASIP 2010)
pages
273 - 280
publisher
IEEE
place of publication
Piscataway, NJ, USA
conference name
2010 Conference on Design and Architectures for Signal and Image Processing (DASIP 2010)
conference location
Edinburgh, Scotland, UK
conference start
2010-10-26
conference end
2010-10-28
Web of Science type
Conference Paper
Web of Science id
11822201
ISBN
9781424487349
9781424487356
DOI
10.1109/DASIP.2010.5706275
language
English
UGent publication?
yes
classification
C1
copyright statement
I have transferred the copyright for this publication to the publisher
id
1111135
handle
http://hdl.handle.net/1854/LU-1111135
date created
2011-01-27 20:04:25
date last changed
2017-01-02 09:52:20
@inproceedings{1111135,
  abstract     = {The power efficiency of an HMCP heavily depends on the architecture of its processor cores. It is thus very important to choose it carefully. When comparing processing architectures for their use in a many-core platform, one must evaluate its IPC, but also its power and area. Precise power and area evaluations can only be done with real implementations. However, comparing processor implementations is a difficult task since the implementation specifities introduce interferences on the performances. This paper proposes a methodology that allows to realize precise comparisons of performance for different processor architectures. Using this methodology, it is possible to choose the best architecture for an HMCP targeting DSP applications. The methodology is based on the use of a common architural template to build the cores, and on the application of specific optimizations when relevant. In order to validate the methodology, three RISC cores are implemented: a single-issue core, and two VLIW processors with respectively 3 and 5 issues. The implemented cores are precisely compared on a set of DSP kernels.},
  author       = {Rousseau, Bertrand and Manet, Philippe and Loiselle, Igor  and Legat, Jean-Didier and Vandierendonck, Hans},
  booktitle    = {2010 Conference on Design and Architectures for Signal and Image Processing (DASIP 2010)},
  isbn         = {9781424487349},
  keyword      = {processor architecture,homogeneous many-core,signal processing,power efficiency},
  language     = {eng},
  location     = {Edinburgh, Scotland, UK},
  pages        = {273--280},
  publisher    = {IEEE},
  title        = {A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms},
  url          = {http://dx.doi.org/10.1109/DASIP.2010.5706275},
  year         = {2010},
}

Chicago
Rousseau, Bertrand, Philippe Manet, Igor Loiselle, Jean-Didier Legat, and Hans Vandierendonck. 2010. “A Methodology for Precise Comparisons of Processor Core Architectures for Homogeneous Many-core DSP Platforms.” In 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP 2010), 273–280. Piscataway, NJ, USA: IEEE.
APA
Rousseau, B., Manet, P., Loiselle, I., Legat, J.-D., & Vandierendonck, H. (2010). A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms. 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP 2010) (pp. 273–280). Presented at the 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP 2010), Piscataway, NJ, USA: IEEE.
Vancouver
1.
Rousseau B, Manet P, Loiselle I, Legat J-D, Vandierendonck H. A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms. 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP 2010). Piscataway, NJ, USA: IEEE; 2010. p. 273–80.
MLA
Rousseau, Bertrand, Philippe Manet, Igor Loiselle, et al. “A Methodology for Precise Comparisons of Processor Core Architectures for Homogeneous Many-core DSP Platforms.” 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP 2010). Piscataway, NJ, USA: IEEE, 2010. 273–280. Print.