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Run-time reconfiguration for automatic hardware/software partitioning

Tom Davidson, Karel Bruneel UGent and Dirk Stroobandt UGent (2010) Proceedings 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010). p.424-429
abstract
Parameterisable configurations allow very fast run-time reconfiguration in FPGAs. The main advantage of this new concept is the automated tool flow that converts a hardware design into a more resource-efficient run-time reconfigurable design without a large design effort. In this paper, we show that the automated tool flow for run-time reconfiguration can be used to easily optimize a full hardware implementation for area by converting it automatically to a hardware/software implementation. This tool flow can partition the design in a very short time and, at the same time, result in significant area gains. The usage of run time reconfiguration allows us to extend the hardware/software boundary so more functionality can be moved to software. We will explain the core principles behind the run-time reconfiguration technique using the AES encoder as an example. For the AES encoder the manual hardware/software partitioning is clear. This manual partitioning will serve as a comparison to the automated partitioning that uses parameterisable configurations. Several possible AES encoder implementations are compared. Our automatically partitioned AES design shows a 20.6 % area gain compared to an unoptimized hardware implementation and a 5.3 % gain compared to a manually optimized 3rd party hardware implementation. In addition, we discuss the results of our technique on other applications, where the hardware/software partitioning is less clear. Among these, a TripleDES implementation shows a 29.3 % area gain using our technique. Based on our AES encoder results, we derive some guidelines for optimizing the impact of parameterisable configurations in general designs.
Please use this url to cite or link to this publication:
author
organization
year
type
conference (conferencePaper)
publication status
published
subject
keyword
hardware/software partitioning, dynamic reconfiguration, AES, FPGA, run-time reconfiguration
in
Proceedings 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010)
editor
V Prasanna, J Becker and R Cumplido
pages
424 - 429
publisher
IEEE Computer Society
place of publication
Los Alamitos, CA, USA
conference name
2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010)
conference location
Cancún, Mexico
conference start
2010-12-13
conference end
2010-12-15
Web of Science type
Conference Paper
Web of Science id
11771988
ISBN
9780769543147
9781424495238
DOI
10.1109/ReConFig.2010.57
language
English
UGent publication?
yes
classification
C1
copyright statement
I have transferred the copyright for this publication to the publisher
id
1105031
handle
http://hdl.handle.net/1854/LU-1105031
date created
2011-01-19 15:01:33
date last changed
2017-01-02 09:52:32
@inproceedings{1105031,
  abstract     = {Parameterisable configurations allow very fast run-time reconfiguration in FPGAs. The main advantage of this new concept is the automated tool flow that converts a hardware design into a more resource-efficient run-time reconfigurable design without a large design effort. In this paper, we show that the automated tool flow for run-time reconfiguration can be used to easily optimize a full hardware implementation for area by converting it automatically to a hardware/software implementation. This tool flow can partition the design in a very short time and, at the same time, result in significant area gains. The usage of run time reconfiguration allows us to extend the hardware/software boundary so more functionality can be moved to software.
We will explain the core principles behind the run-time reconfiguration technique using the AES encoder as an example. For the AES encoder the manual hardware/software partitioning is clear. This manual partitioning will serve as a comparison to the automated partitioning that uses parameterisable configurations. Several possible AES encoder implementations are compared. Our automatically partitioned AES design shows a 20.6 \% area gain compared to an unoptimized hardware implementation and a 5.3 \% gain compared to a manually optimized 3rd party hardware implementation. In addition, we discuss the results of our technique on other applications, where the hardware/software partitioning is less clear. Among these, a TripleDES implementation shows a 29.3 \% area gain using our technique. Based on our AES encoder results, we derive some guidelines for optimizing the impact of parameterisable configurations in general designs.},
  author       = {Davidson, Tom and Bruneel, Karel and Stroobandt, Dirk},
  booktitle    = {Proceedings 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010)},
  editor       = {Prasanna, V and Becker, J and Cumplido, R},
  isbn         = {9780769543147},
  keyword      = {hardware/software partitioning,dynamic reconfiguration,AES,FPGA,run-time reconfiguration},
  language     = {eng},
  location     = {Canc{\'u}n, Mexico},
  pages        = {424--429},
  publisher    = {IEEE Computer Society},
  title        = {Run-time reconfiguration for automatic hardware/software partitioning},
  url          = {http://dx.doi.org/10.1109/ReConFig.2010.57},
  year         = {2010},
}

Chicago
Davidson, Tom, Karel Bruneel, and Dirk Stroobandt. 2010. “Run-time Reconfiguration for Automatic Hardware/software Partitioning.” In Proceedings 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010), ed. V Prasanna, J Becker, and R Cumplido, 424–429. Los Alamitos, CA, USA: IEEE Computer Society.
APA
Davidson, Tom, Bruneel, K., & Stroobandt, D. (2010). Run-time reconfiguration for automatic hardware/software partitioning. In V. Prasanna, J. Becker, & R. Cumplido (Eds.), Proceedings 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010) (pp. 424–429). Presented at the 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010), Los Alamitos, CA, USA: IEEE Computer Society.
Vancouver
1.
Davidson T, Bruneel K, Stroobandt D. Run-time reconfiguration for automatic hardware/software partitioning. In: Prasanna V, Becker J, Cumplido R, editors. Proceedings 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010). Los Alamitos, CA, USA: IEEE Computer Society; 2010. p. 424–9.
MLA
Davidson, Tom, Karel Bruneel, and Dirk Stroobandt. “Run-time Reconfiguration for Automatic Hardware/software Partitioning.” Proceedings 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010). Ed. V Prasanna, J Becker, & R Cumplido. Los Alamitos, CA, USA: IEEE Computer Society, 2010. 424–429. Print.