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A counter architecture for online DVFS profitability estimation

Stijn Eyerman and Lieven Eeckhout UGent (2010) IEEE TRANSACTIONS ON COMPUTERS. 59(11). p.1576-1583
abstract
Dynamic voltage and frequency scaling (DVFS) is a well-known and effective technique for reducing power consumption in modern microprocessors. An important concern though when applying DVFS for online energy and power optimizations is to estimate its profitability in terms of performance and energy. Current DVFS profitability estimation approaches however lack accuracy or incur runtime performance and/or energy overhead. This paper proposes a counter architecture for online DVFS profitability estimation on superscalar out-of-order processors. The counter architecture teases apart the fraction of the execution time that is susceptible to clock frequency versus the fraction that is insusceptible to clock frequency. By doing so, the counter architecture can accurately estimate the performance and energy consumption at different V/f operating points from a single program execution. The DVFS counter architecture estimates performance, energy consumption and ED2P within 0.2%, 0.5% and 0.8% on average, respectively, over a 4× frequency range. Further, the counter architecture incurs a limited hardware cost and is an enabler for online DVFS scheduling both at the intra-core as well as at the inter-core level in a multi-core processor.
Please use this url to cite or link to this publication:
author
organization
year
type
journalArticle (original)
publication status
published
subject
keyword
ENERGY, Computer systems organization, performance of systems, modeling techniques, modeling of computer architecture, PROCESSOR, MICROPROCESSORS, MICROARCHITECTURE, PERFORMANCE, POWER MANAGEMENT, power management
journal title
IEEE TRANSACTIONS ON COMPUTERS
IEEE Trans. Comput.
volume
59
issue
11
pages
1576 - 1583
Web of Science type
Article
Web of Science id
000282091200011
JCR category
COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
JCR impact factor
1.604 (2010)
JCR rank
12/48 (2010)
JCR quartile
2 (2010)
ISSN
0018-9340
DOI
10.1109/TC.2010.65
project
HPC-UGent: the central High Performance Computing infrastructure of Ghent University
language
English
UGent publication?
yes
classification
A1
copyright statement
I have transferred the copyright for this publication to the publisher
id
1087974
handle
http://hdl.handle.net/1854/LU-1087974
date created
2010-12-15 16:38:10
date last changed
2016-12-19 15:45:49
@article{1087974,
  abstract     = {Dynamic voltage and frequency scaling (DVFS) is a well-known and effective technique for reducing power consumption in modern microprocessors. An important concern though when applying DVFS for online energy and power optimizations is to estimate its profitability in terms of performance and energy. Current DVFS profitability estimation approaches however lack accuracy or incur runtime performance and/or energy overhead.
This paper proposes a counter architecture for online DVFS profitability estimation on superscalar out-of-order processors. The counter architecture teases apart the fraction of the execution time that is susceptible to clock frequency versus the fraction that is insusceptible to clock frequency. By doing so, the counter architecture can accurately estimate the performance and energy consumption at different V/f operating points from a single program execution. The DVFS counter architecture estimates performance, energy consumption and ED2P within 0.2\%, 0.5\% and 0.8\% on average, respectively, over a 4{\texttimes} frequency range. Further, the counter architecture incurs a limited hardware cost and is an enabler for online DVFS scheduling both at the intra-core as well as at the inter-core level in a multi-core processor.},
  author       = {Eyerman, Stijn and Eeckhout, Lieven},
  issn         = {0018-9340},
  journal      = {IEEE TRANSACTIONS ON COMPUTERS},
  keyword      = {ENERGY,Computer systems organization,performance of systems,modeling techniques,modeling of computer architecture,PROCESSOR,MICROPROCESSORS,MICROARCHITECTURE,PERFORMANCE,POWER MANAGEMENT,power management},
  language     = {eng},
  number       = {11},
  pages        = {1576--1583},
  title        = {A counter architecture for online DVFS profitability estimation},
  url          = {http://dx.doi.org/10.1109/TC.2010.65},
  volume       = {59},
  year         = {2010},
}

Chicago
Eyerman, Stijn, and Lieven Eeckhout. 2010. “A Counter Architecture for Online DVFS Profitability Estimation.” Ieee Transactions on Computers 59 (11): 1576–1583.
APA
Eyerman, S., & Eeckhout, L. (2010). A counter architecture for online DVFS profitability estimation. IEEE TRANSACTIONS ON COMPUTERS, 59(11), 1576–1583.
Vancouver
1.
Eyerman S, Eeckhout L. A counter architecture for online DVFS profitability estimation. IEEE TRANSACTIONS ON COMPUTERS. 2010;59(11):1576–83.
MLA
Eyerman, Stijn, and Lieven Eeckhout. “A Counter Architecture for Online DVFS Profitability Estimation.” IEEE TRANSACTIONS ON COMPUTERS 59.11 (2010): 1576–1583. Print.