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Developing memory templates for high level synthesis compilers

Craig Truett Moore, Wim Meeus UGent, Harald Devos UGent and Dirk Stroobandt UGent (2010) Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International summer school, Poster abstracts. p.97-100
abstract
We are investigating parametrized memory templates for use with high level synthesis compilers. Each template would have parameters that reflect important trade-offs made during system design, and can be interfaced with external block random access memory (BRAM). The templates would incorporated in our high level synthesis (HLS) compiler, where the template's parameters are adjusted to the application and hardware. Each template would be designed to suite a different type of application. For example we have already made one template for use with a parallel 'for' loops with no loop dependencies and sequential bodies. In the future, we will develop more templates for other types of 'for' loops. We will enhance the compiler so that it can identify the type of application it is compiling and recommend the template best suited for it. The candidate templates will be selected by first matching them against the application's data access pattern with the final decision made using design space exploration of each candidate to find the one with the best performance characteristics.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
keyword
Template, High Level Synthesis, Compiler, FPGA, Memory
in
Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International summer school, Poster abstracts
editor
Koen De Bosschere UGent
pages
97 - 100
publisher
European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC)
conference name
6th International summer school on Advanced Computer Architecture and Complilation for High-Performanc and Embedded Systems (ACACES 2010)
conference location
Terrassa, Spain
conference start
2010-07-11
conference end
2010-07-17
ISBN
9789038216317
language
English
UGent publication?
yes
classification
C1
copyright statement
I have transferred the copyright for this publication to the publisher
id
1077747
handle
http://hdl.handle.net/1854/LU-1077747
date created
2010-11-22 13:37:55
date last changed
2016-12-19 15:34:55
@inproceedings{1077747,
  abstract     = {We are investigating parametrized memory templates for use with high level synthesis compilers. Each template would have parameters that reflect important trade-offs made during system design, and can be interfaced with external block random access memory (BRAM). The templates would incorporated in our high level synthesis (HLS) compiler, where the template's parameters are adjusted to the application and hardware. Each template would be designed to suite a different type of application. For example we have already made one template for use with a parallel 'for' loops with no loop dependencies and sequential bodies. In the future, we will develop more templates for other types of 'for' loops. We will enhance the compiler so that it can identify the type of application it is compiling and recommend the template best suited for it. The candidate templates will be selected by first matching them against the application's data access pattern with the final decision made using design space exploration of each candidate to find the one with the best performance characteristics.},
  author       = {Moore, Craig Truett and Meeus, Wim and Devos, Harald and Stroobandt, Dirk},
  booktitle    = {Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International summer school, Poster abstracts},
  editor       = {De Bosschere, Koen},
  isbn         = {9789038216317},
  keyword      = {Template,High Level Synthesis,Compiler,FPGA,Memory},
  language     = {eng},
  location     = {Terrassa, Spain},
  pages        = {97--100},
  publisher    = {European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC)},
  title        = {Developing memory templates for high level synthesis compilers},
  year         = {2010},
}

Chicago
Moore, Craig Truett, Wim Meeus, Harald Devos, and Dirk Stroobandt. 2010. “Developing Memory Templates for High Level Synthesis Compilers.” In Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International Summer School, Poster Abstracts, ed. Koen De Bosschere, 97–100. European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC).
APA
Moore, C. T., Meeus, W., Devos, H., & Stroobandt, D. (2010). Developing memory templates for high level synthesis compilers. In K. De Bosschere (Ed.), Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International summer school, Poster abstracts (pp. 97–100). Presented at the 6th International summer school on Advanced Computer Architecture and Complilation for High-Performanc and Embedded Systems (ACACES 2010), European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC).
Vancouver
1.
Moore CT, Meeus W, Devos H, Stroobandt D. Developing memory templates for high level synthesis compilers. In: De Bosschere K, editor. Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International summer school, Poster abstracts. European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC); 2010. p. 97–100.
MLA
Moore, Craig Truett, Wim Meeus, Harald Devos, et al. “Developing Memory Templates for High Level Synthesis Compilers.” Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International Summer School, Poster Abstracts. Ed. Koen De Bosschere. European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2010. 97–100. Print.