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An FPGA-based real-time event sampler

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Abstract
This paper presents the design and FPGA-implementation of a sampler that is suited for sampling real-time events in embedded systems. Such sampling is useful, for example, to test whether real-time events are handled in time on such systems. By designing and implementing the sampler as a logic analyzer on an FPGA, several design parameters can be explored and easily modified to match the behavior of different kinds of embedded systems. Moreover, the trade-off between price and performance becomes easy, as it mainly exists of choosing the appropriate type and speed grade of an FPGA family.
Keywords
FPGA, logic analyzer, event sampling, real-time testing

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Chicago
Penneman, Niels, Luc Perneel, Martin Timmerman, and Bjorn De Sutter. 2010. “An FPGA-based Real-time Event Sampler.” In Lecture Notes in Computer Science, ed. Phaophak Sirisuk, Fearghal Morgan, Tarek El-Ghazawi, and Hideharu Amano, 5992:364–371. Berlin, Germany: Springer.
APA
Penneman, N., Perneel, L., Timmerman, M., & De Sutter, B. (2010). An FPGA-based real-time event sampler. In P. Sirisuk, F. Morgan, T. El-Ghazawi, & H. Amano (Eds.), LECTURE NOTES IN COMPUTER SCIENCE (Vol. 5992, pp. 364–371). Presented at the 6th International workshop on Applied Reconfigurable Computing, Berlin, Germany: Springer.
Vancouver
1.
Penneman N, Perneel L, Timmerman M, De Sutter B. An FPGA-based real-time event sampler. In: Sirisuk P, Morgan F, El-Ghazawi T, Amano H, editors. LECTURE NOTES IN COMPUTER SCIENCE. Berlin, Germany: Springer; 2010. p. 364–71.
MLA
Penneman, Niels, Luc Perneel, Martin Timmerman, et al. “An FPGA-based Real-time Event Sampler.” Lecture Notes in Computer Science. Ed. Phaophak Sirisuk et al. Vol. 5992. Berlin, Germany: Springer, 2010. 364–371. Print.
@inproceedings{1076403,
  abstract     = {This paper presents the design and FPGA-implementation of a sampler that is suited for sampling real-time events in embedded systems. Such sampling is useful, for example, to test whether real-time events are handled in time on such systems. By designing and implementing the sampler as a logic analyzer on an FPGA, several design parameters can be explored and easily modi\unmatched{fb01}ed to match the behavior of di\unmatched{fb00}erent kinds of embedded systems. Moreover, the trade-off between price and performance becomes easy, as it mainly exists of choosing the appropriate type and speed grade of an FPGA family.},
  author       = {Penneman, Niels and Perneel, Luc and Timmerman, Martin and De Sutter, Bjorn},
  booktitle    = {LECTURE NOTES IN COMPUTER SCIENCE},
  editor       = {Sirisuk, Phaophak and Morgan, Fearghal and El-Ghazawi, Tarek and Amano, Hideharu},
  isbn         = {9783642121326},
  issn         = {0302-9743},
  keyword      = {FPGA,logic analyzer,event sampling,real-time testing},
  language     = {eng},
  location     = {Bangkok, Thailand},
  pages        = {364--371},
  publisher    = {Springer},
  title        = {An FPGA-based real-time event sampler},
  url          = {http://dx.doi.org/10.1007/978-3-642-12133-3\_35},
  volume       = {5992},
  year         = {2010},
}

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