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A 5-MHz 11-bit delay-based self-oscillating ΣΔ modulator in 0.025 mm2

Bart De Vuyst (UGent) and Pieter Rombouts (UGent)
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Abstract
In this paper a self-oscillating Sigma Delta modulator is presented. By introducing this self-oscillation in the system, the loop filter operates at a speed significantly lower than dictated by the clock frequency. This allows for a simple and power efficient design of the opamps used in the loop filter. The self-oscillation is induced here by introducing a controlled delay in the feedback loop of the modulator. A second order CMOS prototype was constructed in a 0.18 um technology. A clock frequency of 850MHz generates a self-oscillation mode at 106.25 MHz. The modulator achieves a dynamic range (DR) of 66 dB for a signal bandwidth of 5 MHz. The power consumption is only 6mW and the chip area of the modulator core is 0.025mm^2.
Keywords
BANDWIDTH, CLOCK JITTER, ADC, CMOS

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Citation

Please use this url to cite or link to this publication:

Chicago
De Vuyst, Bart, and Pieter Rombouts. 2010. “A 5-MHz 11-bit Delay-based Self-oscillating ΣΔ Modulator in 0.025 Mm2.” In IEEE Custom Integrated Circuits Conference. New York, NY, USA: IEEE.
APA
De Vuyst, Bart, & Rombouts, P. (2010). A 5-MHz 11-bit delay-based self-oscillating ΣΔ modulator in 0.025 mm2. IEEE Custom Integrated Circuits Conference. Presented at the 2010 IEEE Custom Integrated Circuits Conference (CICC 2010), New York, NY, USA: IEEE.
Vancouver
1.
De Vuyst B, Rombouts P. A 5-MHz 11-bit delay-based self-oscillating ΣΔ modulator in 0.025 mm2. IEEE Custom Integrated Circuits Conference. New York, NY, USA: IEEE; 2010.
MLA
De Vuyst, Bart, and Pieter Rombouts. “A 5-MHz 11-bit Delay-based Self-oscillating ΣΔ Modulator in 0.025 Mm2.” IEEE Custom Integrated Circuits Conference. New York, NY, USA: IEEE, 2010. Print.
@inproceedings{1073144,
  abstract     = {In this paper a self-oscillating Sigma Delta modulator is presented. By introducing this self-oscillation in the system, the loop filter operates at a speed significantly lower than dictated by the clock frequency. This allows for a simple and power efficient design of the opamps used in the loop filter. The self-oscillation is induced here by introducing a controlled delay in the feedback loop of the modulator. A second order CMOS prototype was constructed in a 0.18 um technology. A clock frequency of 850MHz generates a self-oscillation mode at 106.25 MHz. The modulator achieves a dynamic range (DR) of 66 dB for a signal bandwidth of 5 MHz. The power consumption is only 6mW and the chip area of the modulator core is 0.025mm\^{ }2.},
  author       = {De Vuyst, Bart and Rombouts, Pieter},
  booktitle    = {IEEE Custom Integrated Circuits Conference},
  isbn         = {9781424457601},
  issn         = {0886-5930},
  keyword      = {BANDWIDTH,CLOCK JITTER,ADC,CMOS},
  language     = {eng},
  location     = {San Jos{\'e}, CA, USA},
  pages        = {4},
  publisher    = {IEEE},
  title        = {A 5-MHz 11-bit delay-based self-oscillating \ensuremath{\Sigma}\ensuremath{\Delta} modulator in 0.025 mm2},
  url          = {http://dx.doi.org/10.1109/CICC.2010.5617589},
  year         = {2010},
}

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