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EEPROM retention time extrapolation from floating gate SILC measurements

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Abstract
This work presents new experimental data on ultra-low level Stress Induced Leakage Currents measured in 7 - 8 nm EEPROM tunnel oxides at room temperature, by using the the floating gate technique. Current-voltage characteristics are successfully modelized by to a one-step tunneling model taking into account the spatial and energetical profiles of defects in SiO2. New phenomena are pointed out, as negative differential resistance and the appearing of threshold voltages below which a rapid decrease of the conduction current is observed. According to our model, these behaviors can be well-simulated considering discrete defects energy levels in the SiO2 bandgap. Threshold voltages measured around 2 to 3 V appear to be very close to retention conditions floating gate potentials in EEPROM cells. According to a simple model, EEPROM retention times are extrapolated and it is shown that the particular behavior of SILC currents could explain the fact that retention times remain in the product specifications even for hardly cycled cells.
Keywords
memory, design, technology

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Chicago
Burignat, Stéphane, Nicolas Baboux, Carole Plossu, and Philippe Boivin. 2005. “EEPROM Retention Time Extrapolation from Floating Gate SILC Measurements.” In Memory Technology and Design, 1st International Conference, Proceedings, 251–254.
APA
Burignat, S., Baboux, N., Plossu, C., & Boivin, P. (2005). EEPROM retention time extrapolation from floating gate SILC measurements. Memory Technology and Design, 1st International conference, Proceedings (pp. 251–254). Presented at the 1st International conference on Memory Technology and Design (ICMTD 2005).
Vancouver
1.
Burignat S, Baboux N, Plossu C, Boivin P. EEPROM retention time extrapolation from floating gate SILC measurements. Memory Technology and Design, 1st International conference, Proceedings. 2005. p. 251–4.
MLA
Burignat, Stéphane, Nicolas Baboux, Carole Plossu, et al. “EEPROM Retention Time Extrapolation from Floating Gate SILC Measurements.” Memory Technology and Design, 1st International Conference, Proceedings. 2005. 251–254. Print.
@inproceedings{1036666,
  abstract     = {This work presents new experimental data on ultra-low level Stress Induced Leakage Currents measured in 7 - 8 nm EEPROM tunnel oxides at room temperature, by using the the floating gate technique. Current-voltage characteristics are successfully modelized by to a one-step tunneling model taking into account the spatial and energetical profiles of defects in SiO2. New phenomena are pointed out, as negative differential resistance and the appearing of threshold voltages below which a rapid decrease of the conduction current is observed. According to our model, these behaviors can be well-simulated considering discrete defects energy levels in the SiO2 bandgap. Threshold voltages measured around 2 to 3 V appear to be very close to retention conditions floating gate potentials in EEPROM cells. According to a simple model, EEPROM retention times are extrapolated and it is shown that the particular behavior of SILC currents could explain the fact that retention times remain in the product specifications even for hardly cycled cells.},
  author       = {Burignat, St{\'e}phane and Baboux, Nicolas and Plossu, Carole and Boivin, Philippe},
  booktitle    = {Memory Technology and Design, 1st International conference, Proceedings},
  keyword      = {memory,design,technology},
  language     = {eng},
  location     = {Giens, France},
  pages        = {251--254},
  title        = {EEPROM retention time extrapolation from floating gate SILC measurements},
  year         = {2005},
}