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Drain/substrate coupling impact on DIBL of ultra thin body and BOX SOI MOSFETs with undoped channel

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Organization
Abstract
For ultimate MOSFET scaling, ultra thin body and BOX SOI transistors have become of great interest, as they are known to dramatically reduce short channel effects (SCE) while maintaining very high device performance. In this work, we emphasize the impact of the substrate / BOX interface space charge conditions on the drain induced barrier lowering (DIBL) increase with gate length reduction, as this drastically changes the channel position in the film and the drain coupling with the channel via substrate and through the BOX. Several modifications to the MASTAR DIBL model are proposed based on ATLAS simulations of the studied structures, in order to explain those effects and fit the experimental data.
Keywords
ATLAS simulations, semiconductor device models, space charge, drain-substrate coupling impact, MOSFET, ultrathin body transistors, drain induced barrier lowering, undoped channel, short channel effects, gate length, interface space charge, silicon-on-insulator, MASTAR DIBL model, Si, BOX SOI MOSFET

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MLA
Burignat, Stéphane, MKM Arshad, J-P Raskin, et al. “Drain/substrate Coupling Impact on DIBL of Ultra Thin Body and BOX SOI MOSFETs with Undoped Channel.” Proceedings of the 39th European Solid-State Device Research Conference. ESSDERC 2009. Ed. D Tsoukalas & A Dimoulas. Piscataway, NJ, USA: IEEE, 2009. 141–144. Print.
APA
Burignat, S., Arshad, M., Raskin, J.-P., Kilchytska, V., Flandre, D., Faynot, O., Scheiblin, P., et al. (2009). Drain/substrate coupling impact on DIBL of ultra thin body and BOX SOI MOSFETs with undoped channel. In D. Tsoukalas & A. Dimoulas (Eds.), Proceedings of the 39th European Solid-State Device Research Conference. ESSDERC 2009 (pp. 141–144). Presented at the 39th European Solid-State Device Research Conference (ESSDERC 2009), Piscataway, NJ, USA: IEEE.
Chicago author-date
Burignat, Stéphane, MKM Arshad, J-P Raskin, V Kilchytska, D Flandre, O Faynot, P Scheiblin, and F Andrieu. 2009. “Drain/substrate Coupling Impact on DIBL of Ultra Thin Body and BOX SOI MOSFETs with Undoped Channel.” In Proceedings of the 39th European Solid-State Device Research Conference. ESSDERC 2009, ed. D Tsoukalas and A Dimoulas, 141–144. Piscataway, NJ, USA: IEEE.
Chicago author-date (all authors)
Burignat, Stéphane, MKM Arshad, J-P Raskin, V Kilchytska, D Flandre, O Faynot, P Scheiblin, and F Andrieu. 2009. “Drain/substrate Coupling Impact on DIBL of Ultra Thin Body and BOX SOI MOSFETs with Undoped Channel.” In Proceedings of the 39th European Solid-State Device Research Conference. ESSDERC 2009, ed. D Tsoukalas and A Dimoulas, 141–144. Piscataway, NJ, USA: IEEE.
Vancouver
1.
Burignat S, Arshad M, Raskin J-P, Kilchytska V, Flandre D, Faynot O, et al. Drain/substrate coupling impact on DIBL of ultra thin body and BOX SOI MOSFETs with undoped channel. In: Tsoukalas D, Dimoulas A, editors. Proceedings of the 39th European Solid-State Device Research Conference. ESSDERC 2009. Piscataway, NJ, USA: IEEE; 2009. p. 141–4.
IEEE
[1]
S. Burignat et al., “Drain/substrate coupling impact on DIBL of ultra thin body and BOX SOI MOSFETs with undoped channel,” in Proceedings of the 39th European Solid-State Device Research Conference. ESSDERC 2009, Athens, Greece, 2009, pp. 141–144.
@inproceedings{1026495,
  abstract     = {{For ultimate MOSFET scaling, ultra thin body and BOX SOI transistors have become of great interest, as they are known to dramatically reduce short channel effects (SCE) while maintaining very high device performance. In this work, we emphasize the impact of the substrate / BOX interface space charge conditions on the drain induced barrier lowering (DIBL) increase with gate length reduction, as this drastically changes the channel position in the film and the drain coupling with the channel via substrate and through the BOX. Several modifications to the MASTAR DIBL model are proposed based on ATLAS simulations of the studied structures, in order to explain those effects and fit the experimental data.}},
  author       = {{Burignat, Stéphane and Arshad, MKM and Raskin, J-P and Kilchytska, V and Flandre, D and Faynot, O and Scheiblin, P and Andrieu, F}},
  booktitle    = {{Proceedings of the 39th European Solid-State Device Research Conference. ESSDERC 2009}},
  editor       = {{Tsoukalas, D and Dimoulas, A}},
  isbn         = {{9781424443512}},
  keywords     = {{ATLAS simulations,semiconductor device models,space charge,drain-substrate coupling impact,MOSFET,ultrathin body transistors,drain induced barrier lowering,undoped channel,short channel effects,gate length,interface space charge,silicon-on-insulator,MASTAR DIBL model,Si,BOX SOI MOSFET}},
  language     = {{eng}},
  location     = {{Athens, Greece}},
  pages        = {{141--144}},
  publisher    = {{IEEE}},
  title        = {{Drain/substrate coupling impact on DIBL of ultra thin body and BOX SOI MOSFETs with undoped channel}},
  url          = {{http://dx.doi.org/10.1109/ESSDERC.2009.5331323}},
  year         = {{2009}},
}

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