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Underlap channel UTBB MOSFETs for low-power analog/RF applications

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Abstract
In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX (UTBB) fully-depleted (FD) SOI MOSFETs to improve analog/RF performance metrics. It is shown that at lower current levels and shorter gate lengths, underlap UTBB MOSFETs can achieve significant improvement > 1.5 times in key analog/RF metrics over devices designed with conventional S/D architecture. Analog/RF figures of merit are analyzed in terms of spacer-to-straggle ratio (s/sigma), a key parameter for the design of underlap devices. Results suggest that underlap S/D design with s/sigma ratio of 3.3 is optimum to enhance analog/RF metrics at low current levels (< 60 muA/mum). The present work provides new viewpoints for realizing future low-power analog devices/circuits with underlap UTBB FETs.

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Chicago
Kranti, A, Stéphane Burignat, J-P Raskin, and GA Armstrong. 2009. “Underlap Channel UTBB MOSFETs for Low-power analog/RF Applications.” In ULIS 2009: 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON, ed. S Mantl, M Lemme, J Schubert, and W Albrecht, 173–176. New York, NY, USA: IEEE.
APA
Kranti, A., Burignat, S., Raskin, J.-P., & Armstrong, G. (2009). Underlap channel UTBB MOSFETs for low-power analog/RF applications. In S. Mantl, M. Lemme, J. Schubert, & W. Albrecht (Eds.), ULIS 2009: 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON (pp. 173–176). Presented at the 2009 10th International Conference on ULtimate Integration on Silicon (ULIS), New York, NY, USA: IEEE.
Vancouver
1.
Kranti A, Burignat S, Raskin J-P, Armstrong G. Underlap channel UTBB MOSFETs for low-power analog/RF applications. In: Mantl S, Lemme M, Schubert J, Albrecht W, editors. ULIS 2009: 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON. New York, NY, USA: IEEE; 2009. p. 173–6.
MLA
Kranti, A, Stéphane Burignat, J-P Raskin, et al. “Underlap Channel UTBB MOSFETs for Low-power analog/RF Applications.” ULIS 2009: 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON. Ed. S Mantl et al. New York, NY, USA: IEEE, 2009. 173–176. Print.
@inproceedings{1026473,
  abstract     = {In this work, we report on the significance of underlap channel architecture in Ultra Thin Body BOX (UTBB) fully-depleted (FD) SOI MOSFETs to improve analog/RF performance metrics. It is shown that at lower current levels and shorter gate lengths, underlap UTBB MOSFETs can achieve significant improvement {\textrangle} 1.5 times in key analog/RF metrics over devices designed with conventional S/D architecture. Analog/RF figures of merit are analyzed in terms of spacer-to-straggle ratio (s/sigma), a key parameter for the design of underlap devices. Results suggest that underlap S/D design with s/sigma ratio of 3.3 is optimum to enhance analog/RF metrics at low current levels ({\textlangle} 60 muA/mum). The present work provides new viewpoints for realizing future low-power analog devices/circuits with underlap UTBB FETs.},
  author       = {Kranti, A and Burignat, St{\'e}phane and Raskin, J-P and Armstrong, GA},
  booktitle    = {ULIS 2009: 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON},
  editor       = {Mantl, S and Lemme, M and Schubert, J and Albrecht, W},
  isbn         = {9781424437054},
  language     = {eng},
  location     = {Aachen, Germany},
  pages        = {173--176},
  publisher    = {IEEE},
  title        = {Underlap channel UTBB MOSFETs for low-power analog/RF applications},
  url          = {http://dx.doi.org/10.1109/ULIS.2009.4897564},
  year         = {2009},
}

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