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Analog/RF performance of sub-100 nm SOI MOSFETs with non-classical gate-source/drain underlap channel design

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Abstract
In this work, we analyze the potential of non-overlap (also known as underlap) source/drain (S/D) channel architecture to improve analog/RF performance metrics of sub-100 nm Ultra Thin Body BOX (UTBB) SOI MOSFETs. It is shown that underlap S/D design results in higher voltage gain (AVO) and cut-off frequency (fT) along with a broader analog `sweet spot' in nanoscale MOSFETs thus offering new possibilities for analog/RF scaling below 60 nm. The advantages offered by underlap channel design are not limited to lower current levels (~10 ¿A/¿m) but extend up to 100 ¿A/¿m which corresponds to optimum AVO and fT performance for most circuit applications. For shorter gate length devices, underlap design results in an impressive 20% improvement in fT along with a 2 fold enhancement in AVO. This work provides new opportunities for realizing future low-power analog/RF design with underlap UTBB MOSFETs.
Keywords
MOSFET, nanoelectronics, source/drain channel architecture, nanoscale MOSFET, higher voltage gain, silicon-on-insulator, analog/RF performance metrics, cut-off frequency, nonclassical gate-source/drain underlap channel design, UTBB SOI MOSFET, ultra thin body box

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Chicago
Kranti, A, R Rashmi, Stéphane Burignat, J-P Raskin, and GA Armstrong. 2010. “Analog/RF Performance of Sub-100 Nm SOI MOSFETs with Non-classical Gate-source/drain Underlap Channel Design.” In 2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 45–48. Piscataway, NJ, USA: IEEE.
APA
Kranti, A., Rashmi, R., Burignat, S., Raskin, J.-P., & Armstrong, G. (2010). Analog/RF performance of sub-100 nm SOI MOSFETs with non-classical gate-source/drain underlap channel design. 2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (pp. 45–48). Presented at the 10th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2010), Piscataway, NJ, USA: IEEE.
Vancouver
1.
Kranti A, Rashmi R, Burignat S, Raskin J-P, Armstrong G. Analog/RF performance of sub-100 nm SOI MOSFETs with non-classical gate-source/drain underlap channel design. 2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. Piscataway, NJ, USA: IEEE; 2010. p. 45–8.
MLA
Kranti, A, R Rashmi, Stéphane Burignat, et al. “Analog/RF Performance of Sub-100 Nm SOI MOSFETs with Non-classical Gate-source/drain Underlap Channel Design.” 2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. Piscataway, NJ, USA: IEEE, 2010. 45–48. Print.
@inproceedings{1026422,
  abstract     = {In this work, we analyze the potential of non-overlap (also known as underlap) source/drain (S/D) channel architecture to improve analog/RF performance metrics of sub-100 nm Ultra Thin Body BOX (UTBB) SOI MOSFETs. It is shown that underlap S/D design results in higher voltage gain (AVO) and cut-off frequency (fT) along with a broader analog `sweet spot' in nanoscale MOSFETs thus offering new possibilities for analog/RF scaling below 60 nm. The advantages offered by underlap channel design are not limited to lower current levels ({\texttildelow}10 {\^A}{\textquestiondown}A/{\^A}{\textquestiondown}m) but extend up to 100 {\^A}{\textquestiondown}A/{\^A}{\textquestiondown}m which corresponds to optimum AVO and fT  performance for most circuit applications. For shorter gate length devices, underlap design results in an impressive 20\% improvement in fT along with a 2 fold enhancement in AVO. This work provides new opportunities for realizing future low-power analog/RF design with underlap UTBB MOSFETs.},
  author       = {Kranti, A and Rashmi, R and Burignat, St{\'e}phane and Raskin, J-P and Armstrong, GA},
  booktitle    = {2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems},
  isbn         = {9781424454563},
  keyword      = {MOSFET,nanoelectronics,source/drain channel architecture,nanoscale MOSFET,higher voltage gain,silicon-on-insulator,analog/RF performance metrics,cut-off frequency,nonclassical gate-source/drain underlap channel design,UTBB SOI MOSFET,ultra thin body box},
  language     = {eng},
  location     = {New Orleans, LA, USA},
  pages        = {45--48},
  publisher    = {IEEE},
  title        = {Analog/RF performance of sub-100 nm SOI MOSFETs with non-classical gate-source/drain underlap channel design},
  url          = {http://dx.doi.org/10.1109/SMIC.2010.5422943},
  year         = {2010},
}

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