Ghent University Academic Bibliography

Advanced

Performance-effective operation below Vcc-min

Nikolas Ladas, Yiannakis Sazeides and Veerle Desmet UGent (2010) 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010). p.223-234
abstract
Continuous circuit miniaturization and increased process variability point to a future with diminishing returns from dynamic voltage scaling. Operation below Vcc-min has been proposed recently as a mean to reverse this trend. The goal of this paper is to minimize the performance loss due to reduced cache capacity when operating below Vcc-min. A simple method is proposed: disable faulty blocks at low voltage. The method is based on observations regarding the distributions of faults in an array according to probability theory. The key lesson, from the probability analysis, is that as the number of uniformly distributed random faulty cells in an array increases the faults increasingly occur in already faulty blocks. The probability analysis is also shown to be useful for obtaining insight about the reliability implications of other cache techniques. For one configuration used in this paper, block disabling is shown to have on the average 6.6% and up to 29% better performance than a previously proposed scheme for low voltage cache operation. Furthermore, block-disabling is simple and less costly to implement and does not degrade performance at or above Vcc-min operation. Finally, it is shown that a victim-cache enables higher and more deterministic performance for a block-disabled cache.
Please use this url to cite or link to this publication:
author
organization
year
type
conference (conferencePaper)
publication status
published
subject
keyword
block-disabled cache, random fault distribution, cache techniques, cache storage, fault diagnosis, arrays, probability, continuous circuit miniaturization, dynamic voltage scaling, probability analysis, probability theory
in
2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010)
pages
223 - 234
publisher
IEEE
place of publication
Piscataway, NJ, USA
conference name
2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010)
conference location
White Plains, NY, USA
conference start
2010-03-28
conference end
2010-03-30
Web of Science type
Conference Paper
Web of Science id
11259894
ISBN
9781424460236
9781424460229
DOI
10.1109/ISPASS.2010.5452017
language
English
UGent publication?
yes
classification
C1
copyright statement
I have transferred the copyright for this publication to the publisher
id
1006881
handle
http://hdl.handle.net/1854/LU-1006881
date created
2010-07-09 08:37:40
date last changed
2017-01-02 09:52:38
@inproceedings{1006881,
  abstract     = {Continuous circuit miniaturization and increased process variability point to a future with diminishing returns from dynamic voltage scaling. Operation below Vcc-min has been proposed recently as a mean to reverse this trend. The goal of this paper is to minimize the performance loss due to reduced cache capacity when operating below Vcc-min. A simple method is proposed: disable faulty blocks at low voltage. The method is based on observations regarding the distributions of faults in an array according to probability theory. The key lesson, from the probability analysis, is that as the number of uniformly distributed random faulty cells in an array increases the faults increasingly occur in already faulty blocks. The probability analysis is also shown to be useful for obtaining insight about the reliability implications of other cache techniques. For one configuration used in this paper, block disabling is shown to have on the average 6.6\% and up to 29\% better performance than a previously proposed scheme for low voltage cache operation. Furthermore, block-disabling is simple and less costly to implement and does not degrade performance at or above Vcc-min operation. Finally, it is shown that a victim-cache enables higher and more deterministic performance for a block-disabled cache.},
  author       = {Ladas, Nikolas and Sazeides, Yiannakis and Desmet, Veerle},
  booktitle    = {2010 IEEE International Symposium on Performance Analysis of Systems \& Software (ISPASS 2010)},
  isbn         = {9781424460236},
  keyword      = {block-disabled cache,random fault distribution,cache techniques,cache storage,fault diagnosis,arrays,probability,continuous circuit miniaturization,dynamic voltage scaling,probability analysis,probability theory},
  language     = {eng},
  location     = {White Plains, NY, USA},
  pages        = {223--234},
  publisher    = {IEEE},
  title        = {Performance-effective operation below Vcc-min},
  url          = {http://dx.doi.org/10.1109/ISPASS.2010.5452017},
  year         = {2010},
}

Chicago
Ladas, Nikolas, Yiannakis Sazeides, and Veerle Desmet. 2010. “Performance-effective Operation Below Vcc-min.” In 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010), 223–234. Piscataway, NJ, USA: IEEE.
APA
Ladas, N., Sazeides, Y., & Desmet, V. (2010). Performance-effective operation below Vcc-min. 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010) (pp. 223–234). Presented at the 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010), Piscataway, NJ, USA: IEEE.
Vancouver
1.
Ladas N, Sazeides Y, Desmet V. Performance-effective operation below Vcc-min. 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010). Piscataway, NJ, USA: IEEE; 2010. p. 223–34.
MLA
Ladas, Nikolas, Yiannakis Sazeides, and Veerle Desmet. “Performance-effective Operation Below Vcc-min.” 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010). Piscataway, NJ, USA: IEEE, 2010. 223–234. Print.