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Continuous circuit miniaturization and increased process variability point to a future with diminishing returns from dynamic voltage scaling. Operation below Vcc-min has been proposed recently as a mean to reverse this trend. The goal of this paper is to minimize the performance loss due to reduced cache capacity when operating below Vcc-min. A simple method is proposed: disable faulty blocks at low voltage. The method is based on observations regarding the distributions of faults in an array according to probability theory. The key lesson, from the probability analysis, is that as the number of uniformly distributed random faulty cells in an array increases the faults increasingly occur in already faulty blocks. The probability analysis is also shown to be useful for obtaining insight about the reliability implications of other cache techniques. For one configuration used in this paper, block disabling is shown to have on the average 6.6% and up to 29% better performance than a previously proposed scheme for low voltage cache operation. Furthermore, block-disabling is simple and less costly to implement and does not degrade performance at or above Vcc-min operation. Finally, it is shown that a victim-cache enables higher and more deterministic performance for a block-disabled cache.
Keywords
block-disabled cache, random fault distribution, cache techniques, cache storage, fault diagnosis, arrays, probability, continuous circuit miniaturization, dynamic voltage scaling, probability analysis, probability theory

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Citation

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Chicago
Ladas, Nikolas, Yiannakis Sazeides, and Veerle Desmet. 2010. “Performance-effective Operation Below Vcc-min.” In 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010), 223–234. Piscataway, NJ, USA: IEEE.
APA
Ladas, N., Sazeides, Y., & Desmet, V. (2010). Performance-effective operation below Vcc-min. 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010) (pp. 223–234). Presented at the 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010), Piscataway, NJ, USA: IEEE.
Vancouver
1.
Ladas N, Sazeides Y, Desmet V. Performance-effective operation below Vcc-min. 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010). Piscataway, NJ, USA: IEEE; 2010. p. 223–34.
MLA
Ladas, Nikolas, Yiannakis Sazeides, and Veerle Desmet. “Performance-effective Operation Below Vcc-min.” 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2010). Piscataway, NJ, USA: IEEE, 2010. 223–234. Print.
@inproceedings{1006881,
  abstract     = {Continuous circuit miniaturization and increased process variability point to a future with diminishing returns from dynamic voltage scaling. Operation below Vcc-min has been proposed recently as a mean to reverse this trend. The goal of this paper is to minimize the performance loss due to reduced cache capacity when operating below Vcc-min. A simple method is proposed: disable faulty blocks at low voltage. The method is based on observations regarding the distributions of faults in an array according to probability theory. The key lesson, from the probability analysis, is that as the number of uniformly distributed random faulty cells in an array increases the faults increasingly occur in already faulty blocks. The probability analysis is also shown to be useful for obtaining insight about the reliability implications of other cache techniques. For one configuration used in this paper, block disabling is shown to have on the average 6.6\% and up to 29\% better performance than a previously proposed scheme for low voltage cache operation. Furthermore, block-disabling is simple and less costly to implement and does not degrade performance at or above Vcc-min operation. Finally, it is shown that a victim-cache enables higher and more deterministic performance for a block-disabled cache.},
  author       = {Ladas, Nikolas and Sazeides, Yiannakis and Desmet, Veerle},
  booktitle    = {2010 IEEE International Symposium on Performance Analysis of Systems \& Software (ISPASS 2010)},
  isbn         = {9781424460236},
  keyword      = {block-disabled cache,random fault distribution,cache techniques,cache storage,fault diagnosis,arrays,probability,continuous circuit miniaturization,dynamic voltage scaling,probability analysis,probability theory},
  language     = {eng},
  location     = {White Plains, NY, USA},
  pages        = {223--234},
  publisher    = {IEEE},
  title        = {Performance-effective operation below Vcc-min},
  url          = {http://dx.doi.org/10.1109/ISPASS.2010.5452017},
  year         = {2010},
}

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