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Scalar vector runahead : removing the shackles of indirect memory chains on in-order cores

Jaime Roelandts (UGent) , Ajeya Naithani (UGent) , Sam Ainsworth, Timothy M. Jones and Lieven Eeckhout (UGent)
(2025) IEEE MICRO. 45(4). p.72-78
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Abstract
Modern processors often face the memory wall as a bottleneck, an exacerbated problem for stall-on-use in-order cores. Despite this limitation, there is growing demand for energy-efficient in-order cores due to privacy and sustainability concerns. Scalar vector runahead (SVR) provides an elegant solution by extracting high memory-level parallelism through piggybacking on existing instructions executed on the processor that lead to future irregular memory accesses. SVR speculatively executes multiple transient, independent, parallel instances of memory accesses and their instruction chains, by initiating memory accesses from many different values of a predicted induction variable. This approach moves mutually independent memory accesses next to each other to hide dependent stalls. With a hardware overhead of only 2 KiB and without the need for hardware vector extensions, SVR delivers 3.2x higher performance than a baseline three-wide in-order core inspired by an Arm Cortex A510, and 1.3x higher performance than an out-of-order core, while halving energy consumption.
Keywords
Registers, Prefetching, Out of order, Detectors, Optimization, Microarchitecture, Training, Hardware, Program processors, Memory management, Energy consumption

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Citation

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MLA
Roelandts, Jaime, et al. “Scalar Vector Runahead : Removing the Shackles of Indirect Memory Chains on in-Order Cores.” IEEE MICRO, vol. 45, no. 4, 2025, pp. 72–78, doi:10.1109/MM.2025.3577524.
APA
Roelandts, J., Naithani, A., Ainsworth, S., Jones, T. M., & Eeckhout, L. (2025). Scalar vector runahead : removing the shackles of indirect memory chains on in-order cores. IEEE MICRO, 45(4), 72–78. https://doi.org/10.1109/MM.2025.3577524
Chicago author-date
Roelandts, Jaime, Ajeya Naithani, Sam Ainsworth, Timothy M. Jones, and Lieven Eeckhout. 2025. “Scalar Vector Runahead : Removing the Shackles of Indirect Memory Chains on in-Order Cores.” IEEE MICRO 45 (4): 72–78. https://doi.org/10.1109/MM.2025.3577524.
Chicago author-date (all authors)
Roelandts, Jaime, Ajeya Naithani, Sam Ainsworth, Timothy M. Jones, and Lieven Eeckhout. 2025. “Scalar Vector Runahead : Removing the Shackles of Indirect Memory Chains on in-Order Cores.” IEEE MICRO 45 (4): 72–78. doi:10.1109/MM.2025.3577524.
Vancouver
1.
Roelandts J, Naithani A, Ainsworth S, Jones TM, Eeckhout L. Scalar vector runahead : removing the shackles of indirect memory chains on in-order cores. IEEE MICRO. 2025;45(4):72–8.
IEEE
[1]
J. Roelandts, A. Naithani, S. Ainsworth, T. M. Jones, and L. Eeckhout, “Scalar vector runahead : removing the shackles of indirect memory chains on in-order cores,” IEEE MICRO, vol. 45, no. 4, pp. 72–78, 2025.
@article{01KAV5NXVGFYFQVQ729PMTGGSS,
  abstract     = {{Modern processors often face the memory wall as a bottleneck, an exacerbated problem for stall-on-use in-order cores. Despite this limitation, there is growing demand for energy-efficient in-order cores due to privacy and sustainability concerns. Scalar vector runahead (SVR) provides an elegant solution by extracting high memory-level parallelism through piggybacking on existing instructions executed on the processor that lead to future irregular memory accesses. SVR speculatively executes multiple transient, independent, parallel instances of memory accesses and their instruction chains, by initiating memory accesses from many different values of a predicted induction variable. This approach moves mutually independent memory accesses next to each other to hide dependent stalls. With a hardware overhead of only 2 KiB and without the need for hardware vector extensions, SVR delivers 3.2x higher performance than a baseline three-wide in-order core inspired by an Arm Cortex A510, and 1.3x higher performance than an out-of-order core, while halving energy consumption.}},
  author       = {{Roelandts, Jaime and Naithani, Ajeya and Ainsworth, Sam and Jones, Timothy M. and Eeckhout, Lieven}},
  issn         = {{0272-1732}},
  journal      = {{IEEE MICRO}},
  keywords     = {{Registers,Prefetching,Out of order,Detectors,Optimization,Microarchitecture,Training,Hardware,Program processors,Memory management,Energy consumption}},
  language     = {{eng}},
  number       = {{4}},
  pages        = {{72--78}},
  title        = {{Scalar vector runahead : removing the shackles of indirect memory chains on in-order cores}},
  url          = {{http://doi.org/10.1109/MM.2025.3577524}},
  volume       = {{45}},
  year         = {{2025}},
}
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