A bit-level double counter enabling power-efficient high-bandwidth VCO-ADCs
- Author
- Simon Ooghe (UGent) , Brendan Saux (UGent) , Tobias Cromheecke (UGent) , Johan Raman (UGent) and Pieter Rombouts (UGent)
- Organization
- Project
- Abstract
- In this brief, a counter structure which facilitates the design of a coarse-fine voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) at high bandwidths is presented. A key challenge is the asynchrony between the coarse and fine counters for which it is quantitatively proven that effective ambiguity resolution is necessary to obtain a sufficient performance. To achieve this, a latch-based, bit-level redundant coarse counter featuring fast ambiguity resolution and operating at high VCO frequencies is presented. Using this novel counter structure a power-efficient VCO-ADC with a core area of 0.007 mm2 and a post-layout simulated figure-of-merit of 168 dB at a bandwidth of 100 MHz is demonstrated.
- Keywords
- VCO, ADC, coarse-fine readout structure, double coarse counter, asynchrony, ambiguity resolution, Voltage-controlled oscillators, Delays, Bandwidth, Latches, Circuits, Power demand, Noise shaping, Decoding, Signal to noise ratio, Costs, DELTA-SIGMA ADC, DESIGN, FOM
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Citation
Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-01K4SGY5QXG17G4363ZHN7K85X
- MLA
- Ooghe, Simon, et al. “A Bit-Level Double Counter Enabling Power-Efficient High-Bandwidth VCO-ADCs.” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 72, no. 9, 2025, pp. 1133–37, doi:10.1109/tcsii.2025.3587495.
- APA
- Ooghe, S., Saux, B., Cromheecke, T., Raman, J., & Rombouts, P. (2025). A bit-level double counter enabling power-efficient high-bandwidth VCO-ADCs. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 72(9), 1133–1137. https://doi.org/10.1109/tcsii.2025.3587495
- Chicago author-date
- Ooghe, Simon, Brendan Saux, Tobias Cromheecke, Johan Raman, and Pieter Rombouts. 2025. “A Bit-Level Double Counter Enabling Power-Efficient High-Bandwidth VCO-ADCs.” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 72 (9): 1133–37. https://doi.org/10.1109/tcsii.2025.3587495.
- Chicago author-date (all authors)
- Ooghe, Simon, Brendan Saux, Tobias Cromheecke, Johan Raman, and Pieter Rombouts. 2025. “A Bit-Level Double Counter Enabling Power-Efficient High-Bandwidth VCO-ADCs.” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 72 (9): 1133–1137. doi:10.1109/tcsii.2025.3587495.
- Vancouver
- 1.Ooghe S, Saux B, Cromheecke T, Raman J, Rombouts P. A bit-level double counter enabling power-efficient high-bandwidth VCO-ADCs. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS. 2025;72(9):1133–7.
- IEEE
- [1]S. Ooghe, B. Saux, T. Cromheecke, J. Raman, and P. Rombouts, “A bit-level double counter enabling power-efficient high-bandwidth VCO-ADCs,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 72, no. 9, pp. 1133–1137, 2025.
@article{01K4SGY5QXG17G4363ZHN7K85X,
abstract = {{In this brief, a counter structure which facilitates the design of a coarse-fine voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) at high bandwidths is presented. A key challenge is the asynchrony between the coarse and fine counters for which it is quantitatively proven that effective ambiguity resolution is necessary to obtain a sufficient performance. To achieve this, a latch-based, bit-level redundant coarse counter featuring fast ambiguity resolution and operating at high VCO frequencies is presented. Using this novel counter structure a power-efficient VCO-ADC with a core area of 0.007 mm2 and a post-layout simulated figure-of-merit of 168 dB at a bandwidth of 100 MHz is demonstrated.}},
author = {{Ooghe, Simon and Saux, Brendan and Cromheecke, Tobias and Raman, Johan and Rombouts, Pieter}},
issn = {{1549-7747}},
journal = {{IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS}},
keywords = {{VCO,ADC,coarse-fine readout structure,double coarse counter,asynchrony,ambiguity resolution,Voltage-controlled oscillators,Delays,Bandwidth,Latches,Circuits,Power demand,Noise shaping,Decoding,Signal to noise ratio,Costs,DELTA-SIGMA ADC,DESIGN,FOM}},
language = {{eng}},
number = {{9}},
pages = {{1133--1137}},
title = {{A bit-level double counter enabling power-efficient high-bandwidth VCO-ADCs}},
url = {{http://doi.org/10.1109/tcsii.2025.3587495}},
volume = {{72}},
year = {{2025}},
}
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