A duty-cycle switching 30-Gb/s burst-mode CDR with 1.6-ns locking time in 28-nm CMOS
- Author
- Xin Wang (UGent) , Achim Vandierendonck (UGent) , Bruno Govaerts (UGent) , Tinus Pannier (UGent) , Warre Geeroms (UGent) , Caro Meysmans (UGent) , Johan Bauwelinck (UGent) and Guy Torfs (UGent)
- Organization
- Project
- Abstract
- This article presents a closed-loop type burst-mode clock and data recovery (BM-CDR) circuit with fast phase offset detection using 8/3x-fractional oversampling in the periodic preamble. The proposed phase offset detector achieves a resolution of 1/8 unit intervals (UIs) with a detection time of 4 UIs. A 2x-oversampling closed-loop bang-bang CDR is performed after the phase offset detection to provide jitter filtering. The switching between these two different oversampling ratios is realized in a single multi-phase clock generator (MPCG) by changing the duty-cycle in four differential quarter-rate clocks. Furthermore, fast duty-cycle switching (DCS) is introduced in the injection-locked ring oscillator (ILRO) design to speed up the transition from one sampling ratio to another. A prototype fabricated in 28-nm CMOS achieves a locking time of 1.6 ns at 30-Gb/s data rate, a BER of 1E-12 with a recovered clock integrated rms jitter of 398.4 fs. The jitter tolerance curve shows a corner frequency around 20 MHz with a 20-dB/dec slope in the low-frequency region. The receiver including the proposed CDR consumes 75.53 mW with 0.9-V supply and occupies an area of 0.148 mm(2).
- Keywords
- Clocks, Logic, Image edge detection, Jitter, Filtering, Accuracy, Detectors, Receivers, Optical switches, Indexes, Burst-mode clock and data recovery (BM-CDR), closed-loop, duty-cycle switching (DCS), fractional oversampling, injection-locked ring oscillator (ILRO), jitter filtering, multi-phase clock generator (MPCG), phase offset detector, DFE RECEIVER, CLOCK
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Citation
Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-01JT2PCJN551KKPPCCJH172WTV
- MLA
- Wang, Xin, et al. “A Duty-Cycle Switching 30-Gb/s Burst-Mode CDR with 1.6-Ns Locking Time in 28-Nm CMOS.” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 61, no. 1, 2026, pp. 318–30, doi:10.1109/JSSC.2025.3556524.
- APA
- Wang, X., Vandierendonck, A., Govaerts, B., Pannier, T., Geeroms, W., Meysmans, C., … Torfs, G. (2026). A duty-cycle switching 30-Gb/s burst-mode CDR with 1.6-ns locking time in 28-nm CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 61(1), 318–330. https://doi.org/10.1109/JSSC.2025.3556524
- Chicago author-date
- Wang, Xin, Achim Vandierendonck, Bruno Govaerts, Tinus Pannier, Warre Geeroms, Caro Meysmans, Johan Bauwelinck, and Guy Torfs. 2026. “A Duty-Cycle Switching 30-Gb/s Burst-Mode CDR with 1.6-Ns Locking Time in 28-Nm CMOS.” IEEE JOURNAL OF SOLID-STATE CIRCUITS 61 (1): 318–30. https://doi.org/10.1109/JSSC.2025.3556524.
- Chicago author-date (all authors)
- Wang, Xin, Achim Vandierendonck, Bruno Govaerts, Tinus Pannier, Warre Geeroms, Caro Meysmans, Johan Bauwelinck, and Guy Torfs. 2026. “A Duty-Cycle Switching 30-Gb/s Burst-Mode CDR with 1.6-Ns Locking Time in 28-Nm CMOS.” IEEE JOURNAL OF SOLID-STATE CIRCUITS 61 (1): 318–330. doi:10.1109/JSSC.2025.3556524.
- Vancouver
- 1.Wang X, Vandierendonck A, Govaerts B, Pannier T, Geeroms W, Meysmans C, et al. A duty-cycle switching 30-Gb/s burst-mode CDR with 1.6-ns locking time in 28-nm CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2026;61(1):318–30.
- IEEE
- [1]X. Wang et al., “A duty-cycle switching 30-Gb/s burst-mode CDR with 1.6-ns locking time in 28-nm CMOS,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 61, no. 1, pp. 318–330, 2026.
@article{01JT2PCJN551KKPPCCJH172WTV,
abstract = {{This article presents a closed-loop type burst-mode clock and data recovery (BM-CDR) circuit with fast phase offset detection using 8/3x-fractional oversampling in the periodic preamble. The proposed phase offset detector achieves a resolution of 1/8 unit intervals (UIs) with a detection time of 4 UIs. A 2x-oversampling closed-loop bang-bang CDR is performed after the phase offset detection to provide jitter filtering. The switching between these two different oversampling ratios is realized in a single multi-phase clock generator (MPCG) by changing the duty-cycle in four differential quarter-rate clocks. Furthermore, fast duty-cycle switching (DCS) is introduced in the injection-locked ring oscillator (ILRO) design to speed up the transition from one sampling ratio to another. A prototype fabricated in 28-nm CMOS achieves a locking time of 1.6 ns at 30-Gb/s data rate, a BER of 1E-12 with a recovered clock integrated rms jitter of 398.4 fs. The jitter tolerance curve shows a corner frequency around 20 MHz with a 20-dB/dec slope in the low-frequency region. The receiver including the proposed CDR consumes 75.53 mW with 0.9-V supply and occupies an area of 0.148 mm(2).}},
author = {{Wang, Xin and Vandierendonck, Achim and Govaerts, Bruno and Pannier, Tinus and Geeroms, Warre and Meysmans, Caro and Bauwelinck, Johan and Torfs, Guy}},
issn = {{0018-9200}},
journal = {{IEEE JOURNAL OF SOLID-STATE CIRCUITS}},
keywords = {{Clocks,Logic,Image edge detection,Jitter,Filtering,Accuracy,Detectors,Receivers,Optical switches,Indexes,Burst-mode clock and data recovery (BM-CDR),closed-loop,duty-cycle switching (DCS),fractional oversampling,injection-locked ring oscillator (ILRO),jitter filtering,multi-phase clock generator (MPCG),phase offset detector,DFE RECEIVER,CLOCK}},
language = {{eng}},
number = {{1}},
pages = {{318--330}},
title = {{A duty-cycle switching 30-Gb/s burst-mode CDR with 1.6-ns locking time in 28-nm CMOS}},
url = {{http://doi.org/10.1109/JSSC.2025.3556524}},
volume = {{61}},
year = {{2026}},
}
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