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A 200-256-GS/s current-mode 4-way interleaved sampling front-end with over 67-GHz bandwidth using a slew-rate insensitive clocking scheme

Shengpu Niu (UGent) , Joris Lambrecht (UGent) , Cheng Wang (UGent) , Michiel Verplaetse, Ye Gu (UGent) , Gertjan Coudyzer (UGent) and Xin Yin (UGent)
(2025) IEEE JOURNAL OF SOLID-STATE CIRCUITS. 60(1). p.244-259
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Abstract
The surge of data traffic in emerging optical communication applications has led to the development of ultra-fast transceivers with extremely high data throughput. The latest transmitters and receivers aim for symbol rates of 150-200 Gbaud or even higher, striving to achieve band-widths beyond 70 GHz. However, the current state-of-the-artanalog-to-digital converters (ADCs) in advanced CMOS-FinFET technologies can only handle limited analog input bandwidths and sampling rates, becoming a bottleneck in enhancing the overall speed of the transceiver. A time-interleaved sampling front-end acting as an input signal de-interleaver can reduce the sub-ADCs' analog bandwidth and clock jitter requirements. This article investigates a current-mode time-interleaved 1-4 sampling front-end operating at 200-256 GS/s, using a 50% duty-cycle slew-rate insensitive quadrature clocking strategy. The chip was fabricated in a 130-nm SiGe BiCMOS technology and was characterized by single-tone sinusoidal and non-return-to-zero/pulse-amplitude- modulation-4-level (NRZ/PAM-4)measurements at 200, 224, and 256 GS/s. The chip demonstratesa 3-dB analog input bandwidth beyond 67 GHz and a signal-to-noise-and-distortion ratio (SNDR) of 27.8-34.1 dB (at 200 GS/s),25-36.3 dB (at 224 GS/s), and 22.3-39 dB (at 256 GS/s) for input frequencies from 1.1 to 67.1 GHz. The analog demultiplexing functionality of the sampling front-end is demonstrated with 100,112, and 128 Gbaud NRZ/PAM-4 measurements. The completechip consumes a power of 1.1 W at 256 GS/s, corresponding to an efficiency of 4.3 pJ/sample or 4.3 pJ/bit (with two samplesper symbol).
Keywords
BiCMOS integrated circuits, current-mode sampling, demultiplexing, high-speed interleaved sampler, COUPLED SLOTLINE MODE, CPW

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MLA
Niu, Shengpu, et al. “A 200-256-GS/s Current-Mode 4-Way Interleaved Sampling Front-End with over 67-GHz Bandwidth Using a Slew-Rate Insensitive Clocking Scheme.” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 60, no. 1, 2025, pp. 244–59, doi:10.1109/JSSC.2024.3416528.
APA
Niu, S., Lambrecht, J., Wang, C., Verplaetse, M., Gu, Y., Coudyzer, G., & Yin, X. (2025). A 200-256-GS/s current-mode 4-way interleaved sampling front-end with over 67-GHz bandwidth using a slew-rate insensitive clocking scheme. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 60(1), 244–259. https://doi.org/10.1109/JSSC.2024.3416528
Chicago author-date
Niu, Shengpu, Joris Lambrecht, Cheng Wang, Michiel Verplaetse, Ye Gu, Gertjan Coudyzer, and Xin Yin. 2025. “A 200-256-GS/s Current-Mode 4-Way Interleaved Sampling Front-End with over 67-GHz Bandwidth Using a Slew-Rate Insensitive Clocking Scheme.” IEEE JOURNAL OF SOLID-STATE CIRCUITS 60 (1): 244–59. https://doi.org/10.1109/JSSC.2024.3416528.
Chicago author-date (all authors)
Niu, Shengpu, Joris Lambrecht, Cheng Wang, Michiel Verplaetse, Ye Gu, Gertjan Coudyzer, and Xin Yin. 2025. “A 200-256-GS/s Current-Mode 4-Way Interleaved Sampling Front-End with over 67-GHz Bandwidth Using a Slew-Rate Insensitive Clocking Scheme.” IEEE JOURNAL OF SOLID-STATE CIRCUITS 60 (1): 244–259. doi:10.1109/JSSC.2024.3416528.
Vancouver
1.
Niu S, Lambrecht J, Wang C, Verplaetse M, Gu Y, Coudyzer G, et al. A 200-256-GS/s current-mode 4-way interleaved sampling front-end with over 67-GHz bandwidth using a slew-rate insensitive clocking scheme. IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2025;60(1):244–59.
IEEE
[1]
S. Niu et al., “A 200-256-GS/s current-mode 4-way interleaved sampling front-end with over 67-GHz bandwidth using a slew-rate insensitive clocking scheme,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 60, no. 1, pp. 244–259, 2025.
@article{01J2ZR6SJFYVD6V8NDA5QTYZS4,
  abstract     = {{The surge of data traffic in emerging optical communication applications has led to the development of ultra-fast transceivers with extremely high data throughput. The latest transmitters and receivers aim for symbol rates of 150-200 Gbaud or even higher, striving to achieve band-widths beyond 70 GHz. However, the current state-of-the-artanalog-to-digital converters (ADCs) in advanced CMOS-FinFET technologies can only handle limited analog input bandwidths and sampling rates, becoming a bottleneck in enhancing the overall speed of the transceiver. A time-interleaved sampling front-end acting as an input signal de-interleaver can reduce the sub-ADCs' analog bandwidth and clock jitter requirements. This article investigates a current-mode time-interleaved 1-4 sampling front-end operating at 200-256 GS/s, using a 50% duty-cycle slew-rate insensitive quadrature clocking strategy. The chip was fabricated in a 130-nm SiGe BiCMOS technology and was characterized by single-tone sinusoidal and non-return-to-zero/pulse-amplitude- modulation-4-level (NRZ/PAM-4)measurements at 200, 224, and 256 GS/s. The chip demonstratesa 3-dB analog input bandwidth beyond 67 GHz and a signal-to-noise-and-distortion ratio (SNDR) of 27.8-34.1 dB (at 200 GS/s),25-36.3 dB (at 224 GS/s), and 22.3-39 dB (at 256 GS/s) for input frequencies from 1.1 to 67.1 GHz. The analog demultiplexing functionality of the sampling front-end is demonstrated with 100,112, and 128 Gbaud NRZ/PAM-4 measurements. The completechip consumes a power of 1.1 W at 256 GS/s, corresponding to an efficiency of 4.3 pJ/sample or 4.3 pJ/bit (with two samplesper symbol).}},
  author       = {{Niu, Shengpu and Lambrecht, Joris and Wang, Cheng and Verplaetse, Michiel and Gu, Ye and Coudyzer, Gertjan and Yin, Xin}},
  issn         = {{0018-9200}},
  journal      = {{IEEE JOURNAL OF SOLID-STATE CIRCUITS}},
  keywords     = {{BiCMOS integrated circuits,current-mode sampling,demultiplexing,high-speed interleaved sampler,COUPLED SLOTLINE MODE,CPW}},
  language     = {{eng}},
  number       = {{1}},
  pages        = {{244--259}},
  title        = {{A 200-256-GS/s current-mode 4-way interleaved sampling front-end with over 67-GHz bandwidth using a slew-rate insensitive clocking scheme}},
  url          = {{http://doi.org/10.1109/JSSC.2024.3416528}},
  volume       = {{60}},
  year         = {{2025}},
}
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