Influence of drain and gate potential on gate failure in semi-vertical GaN-on-Si trench MOSFETs
- Author
- D. Favero, C. De Santi, K. Mukherjee, K. Geens, M. Borga, Benoit Bakeroot (UGent) , S. You, S. Decoutere, G. Meneghesso, E. Zanoni and M. Meneghini
- Organization
- Abstract
- In this work, a detailed analysis of degradation and failure of semi-vertical GaN-on-Si trench MOSFETs is reported. OFF-state, semi-ON state and ON-state conditions were analyzed, to evaluate how the gate and drain bias can impact on the failure voltage. We demonstrate that: a) devices with a bilayer gate insulator (2.5 nm Al2O3 interface dielectric to GaN, + 35 nm SiO2 main dielectric) have a superior performance, compared to single-insulator (35 nm Al2O3) samples; b) in a drain step-stress, the gate voltage (resulting in different operating regimes, OFF, semi-ON or ON-state) can significantly impact on the failure voltage of the devices; c) stress at high V-GS and/or V-DS may induce a significant shift in threshold voltage, which is stronger when the devices are stressed in the ON-state. The results - complemented by 2D simulations - provide a description of the factors limiting the breakdown robustness of GaN vertical transistors.
- Keywords
- GaN-on-Si, Gate failure, Gate stack, Semi-vertical GaN, CAPACITORS
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Citation
Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-01HTHK6KABT5C9ST4Z183ZNJC3
- MLA
- Favero, D., et al. “Influence of Drain and Gate Potential on Gate Failure in Semi-Vertical GaN-on-Si Trench MOSFETs.” 2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), IEEE, 2022, doi:10.1109/IRPS48227.2022.9764600.
- APA
- Favero, D., De Santi, C., Mukherjee, K., Geens, K., Borga, M., Bakeroot, B., … Meneghini, M. (2022). Influence of drain and gate potential on gate failure in semi-vertical GaN-on-Si trench MOSFETs. 2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). Presented at the IEEE International Reliability Physics Symposium (IRPS), Dallas, TX. https://doi.org/10.1109/IRPS48227.2022.9764600
- Chicago author-date
- Favero, D., C. De Santi, K. Mukherjee, K. Geens, M. Borga, Benoit Bakeroot, S. You, et al. 2022. “Influence of Drain and Gate Potential on Gate Failure in Semi-Vertical GaN-on-Si Trench MOSFETs.” In 2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). IEEE. https://doi.org/10.1109/IRPS48227.2022.9764600.
- Chicago author-date (all authors)
- Favero, D., C. De Santi, K. Mukherjee, K. Geens, M. Borga, Benoit Bakeroot, S. You, S. Decoutere, G. Meneghesso, E. Zanoni, and M. Meneghini. 2022. “Influence of Drain and Gate Potential on Gate Failure in Semi-Vertical GaN-on-Si Trench MOSFETs.” In 2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). IEEE. doi:10.1109/IRPS48227.2022.9764600.
- Vancouver
- 1.Favero D, De Santi C, Mukherjee K, Geens K, Borga M, Bakeroot B, et al. Influence of drain and gate potential on gate failure in semi-vertical GaN-on-Si trench MOSFETs. In: 2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). IEEE; 2022.
- IEEE
- [1]D. Favero et al., “Influence of drain and gate potential on gate failure in semi-vertical GaN-on-Si trench MOSFETs,” in 2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), Dallas, TX, 2022.
@inproceedings{01HTHK6KABT5C9ST4Z183ZNJC3,
abstract = {{In this work, a detailed analysis of degradation and failure of semi-vertical GaN-on-Si trench MOSFETs is reported. OFF-state, semi-ON state and ON-state conditions were analyzed, to evaluate how the gate and drain bias can impact on the failure voltage. We demonstrate that: a) devices with a bilayer gate insulator (2.5 nm Al2O3 interface dielectric to GaN, + 35 nm SiO2 main dielectric) have a superior performance, compared to single-insulator (35 nm Al2O3) samples; b) in a drain step-stress, the gate voltage (resulting in different operating regimes, OFF, semi-ON or ON-state) can significantly impact on the failure voltage of the devices; c) stress at high V-GS and/or V-DS may induce a significant shift in threshold voltage, which is stronger when the devices are stressed in the ON-state. The results - complemented by 2D simulations - provide a description of the factors limiting the breakdown robustness of GaN vertical transistors.}},
author = {{Favero, D. and De Santi, C. and Mukherjee, K. and Geens, K. and Borga, M. and Bakeroot, Benoit and You, S. and Decoutere, S. and Meneghesso, G. and Zanoni, E. and Meneghini, M.}},
booktitle = {{2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)}},
isbn = {{9781665479509}},
issn = {{1541-7026}},
keywords = {{GaN-on-Si,Gate failure,Gate stack,Semi-vertical GaN,CAPACITORS}},
language = {{eng}},
location = {{Dallas, TX}},
pages = {{4}},
publisher = {{IEEE}},
title = {{Influence of drain and gate potential on gate failure in semi-vertical GaN-on-Si trench MOSFETs}},
url = {{http://doi.org/10.1109/IRPS48227.2022.9764600}},
year = {{2022}},
}
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