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Decoupled vector runahead

Ajeya Naithani (UGent) , Jaime Roelandts (UGent) , Sam Ainsworth, Timothy M. Jones and Lieven Eeckhout (UGent)
(2023) 56TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2023. p.17-31
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Organization
Abstract
We present Decoupled Vector Runahead (DVR), an in-core prefetching technique, executing separately to the main application thread, that exploits massive amounts of memory-level parallelism to improve the performance of applications featuring indirect memory accesses. DVR dynamically infers loop bounds at run-time, recognizing striding loads, and vectorizing subsequent instructions that are part of an indirect chain. It proactively issues memory accesses for the resulting loads far into the future, even when the out-of-order core has not yet stalled, bringing their data into the L1 cache, and thus providing timely prefetches for the main thread. DVR can adjust the degree of vectorization at run-time, vectorize the same chain of indirect memory accesses across multiple invocations of an inner loop, and efficiently handle branch divergence along the vectorized chain. DVR runs as an on-demand, speculative, in-order, lightweight hardware subthread alongside the main thread within the core and incurs a minimal hardware overhead of only 1139 bytes. Relative to a large superscalar 5-wide out-of-order baseline and Vector Runahead — a recent microarchitectural technique to accelerate indirect memory accesses on out-of-order processors — DVR delivers 2.4 × and 2 × higher performance, respectively, for a set of graph analytics, database, and HPC workloads.
Keywords
graph processing, speculative vectorization, runahead, prefetching, CPU microarchitecture

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MLA
Naithani, Ajeya, et al. “Decoupled Vector Runahead.” 56TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2023, Association for Computing Machinery (ACM), 2023, pp. 17–31, doi:10.1145/3613424.3614255.
APA
Naithani, A., Roelandts, J., Ainsworth, S., Jones, T. M., & Eeckhout, L. (2023). Decoupled vector runahead. 56TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2023, 17–31. https://doi.org/10.1145/3613424.3614255
Chicago author-date
Naithani, Ajeya, Jaime Roelandts, Sam Ainsworth, Timothy M. Jones, and Lieven Eeckhout. 2023. “Decoupled Vector Runahead.” In 56TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2023, 17–31. New York: Association for Computing Machinery (ACM). https://doi.org/10.1145/3613424.3614255.
Chicago author-date (all authors)
Naithani, Ajeya, Jaime Roelandts, Sam Ainsworth, Timothy M. Jones, and Lieven Eeckhout. 2023. “Decoupled Vector Runahead.” In 56TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2023, 17–31. New York: Association for Computing Machinery (ACM). doi:10.1145/3613424.3614255.
Vancouver
1.
Naithani A, Roelandts J, Ainsworth S, Jones TM, Eeckhout L. Decoupled vector runahead. In: 56TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2023. New York: Association for Computing Machinery (ACM); 2023. p. 17–31.
IEEE
[1]
A. Naithani, J. Roelandts, S. Ainsworth, T. M. Jones, and L. Eeckhout, “Decoupled vector runahead,” in 56TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2023, Toronto, Canada, 2023, pp. 17–31.
@inproceedings{01HMR8HPGNZS1RC118QA1GPBMG,
  abstract     = {{We present Decoupled Vector Runahead (DVR), an in-core prefetching technique, executing separately to the main application thread, that exploits massive amounts of memory-level parallelism to improve the performance of applications featuring indirect memory accesses. DVR dynamically infers loop bounds at run-time, recognizing striding loads, and vectorizing subsequent instructions that are part of an indirect chain. It proactively issues memory accesses for the resulting loads far into the future, even when the out-of-order core has not yet stalled, bringing their data into the L1 cache, and thus providing timely prefetches for the main thread. DVR can adjust the degree of vectorization at run-time, vectorize the same chain of indirect memory accesses across multiple invocations of an inner loop, and efficiently handle branch divergence along the vectorized chain. DVR runs as an on-demand, speculative, in-order, lightweight hardware subthread alongside the main thread within the core and incurs a minimal hardware overhead of only 1139 bytes. Relative to a large superscalar 5-wide out-of-order baseline and Vector Runahead — a recent microarchitectural technique to accelerate indirect memory accesses on out-of-order processors — DVR delivers 2.4 × and 2 × higher performance, respectively, for a set of graph analytics, database, and HPC workloads.}},
  author       = {{Naithani, Ajeya and Roelandts, Jaime and Ainsworth, Sam and Jones, Timothy M. and Eeckhout, Lieven}},
  booktitle    = {{56TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2023}},
  isbn         = {{9798400703294}},
  keywords     = {{graph processing,speculative vectorization,runahead,prefetching,CPU microarchitecture}},
  language     = {{eng}},
  location     = {{Toronto, Canada}},
  pages        = {{17--31}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{Decoupled vector runahead}},
  url          = {{http://doi.org/10.1145/3613424.3614255}},
  year         = {{2023}},
}
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