Yun Zhou
- ORCID iD
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0000-0001-5879-6142
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RapidStream 2.0 : automated parallel implementation of latency insensitive FPGA designs through partial reconfiguration
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- PhD Thesis
- open access
FPGA placement and routing : from academia to industry
(2022) -
- Conference Paper
- C1
- open access
RapidStream : parallel physical implementation of FPGA HLS designs
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RWRoute : an open-source timing-driven router for commercial FPGAs
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Accelerating FPGA routing through algorithmic enhancements and connection-aware parallelization
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On the exploration of connection-aware partitioning for parallel FPGA routing
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A new adaptation of particle swarm optimization applied to modern FPGA placement
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MODA-PSO : towards fast hard block legalization for analytical FPGA placement