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Precise runahead execution
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Adaptive memory-side last-level GPU caching
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Racing to hardware-validated simulation
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Modeling emerging memory-divergent GPU applications
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Precise runahead execution
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Architectural support for probabilistic branches
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Maximizing heterogeneous processor performance under power constraints
(2018) -
LA-LLC : inter-core locality-aware last-level cache to exploit many-to-many traffic in GPGPUs
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Maximizing heterogeneous processor performance under power constraints