dr. ir. Marijn Verbeke
- Work address
-
Technologiepark Zwijnaarde 126
9052 Zwijnaarde - Marijn.Verbeke@UGent.be
- ORCID iD
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0000-0001-5878-706X
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- Journal Article
- A1
- open access
A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs
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- Journal Article
- A1
- open access
A 1.8-pJ/b, 12.5-25-Gb/s wide range all-digital clock and data recovery circuit
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- PhD Thesis
- open access
Low-power subsampling all-digital clock and data recovery techniques for multi-gigabit passive optical networks
(2018) -
- PhD Thesis
- open access
Low-Power Subsampling All-Digital Clock and Data Recovery Techniques for Multi-Gigabit Passive Optical Networks
(2017) -
- Conference Paper
- P1
- open access
A 25 Gb/s all-digital clock and data recovery circuit for burst mode applications in PONs
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- Conference Paper
- C3
- open access
Influence of jitter on limit cycles in bang-bang clock and data recovery circuits
(2016) p.1-1 -
- Journal Article
- A1
- open access
Inverse Alexander phase detector
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- Conference Paper
- C1
- open access
A low power 40 Gbit/s cascaded extension to bit-interleaving optical networks enabling next-generation metro/access connectivity
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- Conference Paper
- C3
- open access
Fast determination of instability in a nonlinear Clock and Data Recovery circuit
(2015) -
- Conference Paper
- P1
- open access
Voltage controlled oscillators for 40Gbit/s cascaded bit-interleaving PON