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Improving the gain and reducing the overhead of dynamic circuit specialisation and microreconfiguration
(2015) -
Enabling FPGA routing configuration sharing in dynamic partial reconfiguration
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- Conference Paper
- P1
- open access
Estimating circuit delays in FPGAs after technology mapping
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On the impact of replacing low-speed configuration buses on FPGAs with the chip’s internal configuration infrastructure
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TCONMAP: technology mapping for parameterised FPGA configurations
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Avoiding transitional effects in dynamic circuit specialisation on FPGAs
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- Journal Article
- A1
- open access
Identification of dynamic circuit specialization opportunities in RTL code
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FASTER: facilitating analysis and synthesis technologies for effective reconfiguration
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Reducing the overhead of dynamic partial reconfiguration for multi-mode circuits
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Improving reconfiguration speed for dynamic circuit specialization using placement constraints