Academic Bibliography

Search 200 years of publications by Ghent University researchers.

Jo Pletinckx

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- Conference Paper
- P1
Web-based embedded control platform

Zhe Lou, Jo Pletinckx, Stefaan Verschuere, X QIU and Jan Vandewege (UGent)

(2003) PROCEEDINGS OF THE 3RD IEEE INTERNATIONAL SYMPOSIUM ON SIGNAL PROCESSING AND INFORMATION TECHNOLOGY. p.58-61
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- Conference Paper
- C1
Web-based embedded control platform

Zhe Lou, Jo Pletinckx, Stefaan Verschuere, Xing-Zhi Qiu (UGent) and Jan Vandewege (UGent)

(2003) Proceedings of ISSPIT 2003.
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- Conference Paper
- C1
Real-time twisted pair line emulation

Jo Pletinckx and Jan Vandewege (UGent)

(2003) Fourth FTW PhD Symposium, Faculty of Engineering, Ghent University.
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A Java-based embedded digital signal processing system

Zhe Lou, Stefaan Verschuere, Jo Pletinckx, Xing-Zhi Qiu (UGent) and Jan Vandewege (UGent)

(2003) Digest of the proceedings of the Wseas Conferences august, september, october 2003.
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- Conference Paper
- C1
A novel low-memory SPIHT codec for embedded progressive wavelet-based image compression

Zhe Lou, Xing-Zhi Qiu (UGent) , Stefaan Verschuere, Jo Pletinckx and Jan Vandewege (UGent)

(2003) See how signal processing touches your life every day..
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- Book Chapter
A Java-Based Embedded Digital Signal Processing System

Zhe Lou, Stefaan Verschuere, Jo Pletinckx, Xing-Zhi Qiu (UGent) and Jan Vandewege (UGent)

(2003) Wseas Transactions on Computers. p.851-854
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- Journal Article
- A2
Creating quasistatic,parameterized FPGA designs

Jo Pletinckx, R VLAMINCK and Jan Vandewege (UGent)

(2003) EDN Europe. 48(7). p.53-55
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- Journal Article
- A1
Creating quasistatic, parameterized FPGA designs

Jo Pletinckx, R VLAMINCK and Jan Vandewege (UGent)

(2003) EDN. 48(17).
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- Book Chapter
A fixed point optimisation scheme for direct form IIR filters.

Jo Pletinckx, Rik Vlaminck, Stefaan Verschuere, Stijn Bertrem, Jan Vandewege (UGent) and S TEMMERMAN

(2002) A series of Reference Books and Textbooks, Electrical and Computer Engineering Series, Recent Advances in Circuits, Systems and Signal Processing, 2002. p.18-22
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- Conference Paper
- C1
FPGA based real-time constrained time area optimized IIR design using digital-serial arithmetic

Rik Vlaminck, Jo Pletinckx, Stefaan Verschuere, Stijn Bertrem, Jan Vandewege (UGent) , P BOETS, G VANUYTSEL and S TEMMERMAN

(2002) Proceedings (on cd-rom) of the 6th WSEAS CSCC Multiconference, CSCC'2002, 7-14 July 2002, Rethymnon, Crete Island, Greece, paper 716 (5 pages). -.

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