Henk Neefs
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Designing a branch predictor for a block structured architecture
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On the Feasibility of Fixed-Length Block Structured Architectures.
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Performance Analysis through Synthetic Trace Generation
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Estimating IPC of a Block Structured Instruction Set Architecture in an Early Design Stage. Parallel Computing: Fundamentals and Applications ;.
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Optoelectronic interconnects for integrated circuits. Achievements 1996-2000.
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A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks.
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Early design stage exploration of fixed-length block structured architectures.
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On the Benefits of a Block Structured Instruction Set Architecture.
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On the Organization and Implementation of a Fixed-Length Block Structured Instruction Set Architecture.
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Investigating the Implementation of a Block Structured Processor Architecture in an Early Design Stage.
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Exploitable levels of ILP in future processors.
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Latency requirements of optical interconnects at different memory hierarchy levels of a computer system
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Aspects of a Fixed-Length Block Structured Instruction Set to Improve Loop Performance
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Improving Loop Performance on a Block Structured Architecture through Predication
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A Quantitative Study of Optical Interconnects at the L2-cache to Main Memory Level in a Uniprocessor
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Optical Interconnects at the L2 Cache to Main Memory Level in a Computer System and the Effect of Prefetching
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Latency Requirements of Optical Interconnects at Different Memory Hierarchy Levels of a Computer System
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ESCAPE: Environment for the Simulation of Computer Architectures for the Purpose of Education
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An Analytical Model for Performance Estimation of Modern Data-Flow Style Scheduling Microprocessors
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Microarchitectural Issues of a Fixed Length Block Structured Instruction Set Architecture
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Issues in Compilation for Fixed-Length Block Structured Instruction Set Architectures
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A C++ Simulator modelling a modern data-flow scheduling Microprocessor
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Simulating a Modern Data-flow Scheduling Microprocessor in C++
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A Microarchitecture for a fixed length Block Structured instruction set Architecture
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Arrays of light emitting diodes with integrated diffractive microlenses for board-to-board optical interconnect applications: design, modelling and experimental assessment.
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A Optoelectronic 3-D Field Programmable Gate Arra. , Prague, 1994.