ereprof. dr. ir. Erik D'Hollander
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Exploring large language models for HDL verilog
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ZyPy : intercepting NumPy operations for acceleration on FPGAs
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Accelerating python numerical libraries using FPGAs
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Empowering parallel computing with field programmable gate arrays
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Mapping a guided image filter on the HARP reconfigurable architecture using OpenCL
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Exploring Opencl on a CPU-FPGA heterogeneous architecture research platform (HARP)
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Heterogeneous cloud computing : design methodology to combine hardware accelerators
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Remote Procedure Call compiler for Field-Programmable Gate Arrays
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ParaFPGA 2017 : enlarging the scope of parallel programming with FPGAs
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Calling hardware procedures in a reconfigurable accelerator using RPC-FPGA
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ParaFPGA15 : exploring threads and trends in programmable hardware
(2016) PARALLEL COMPUTING : ON THE ROAD TO EXASCALE. In Advances in Parallel Computing 27. p.501-504 -
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High-level synthesis optimization for blocked floating-point matrix multiplication
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High-level synthesis for FPGAs, the Swiss army knife for high-performance computing
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Performance and resource modeling for FPGAs using high-level synthesis tools
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ParaFPGA 2013 : harnessing programs, power and performance in parallel FPGA applications
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Exploiting high-level synthesis tools for high-performance applications on FPGAs
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Comparing and combining GPU and FPGA accelerators in an image processing context
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Performance and programming environment of a combined GPU/FPGA desktop
(2013) Transition of HPC towards exascale computing. In Advances in Parallel Computing 24. p.177-193 -
Transition of HPC towards exascale computing
Erik D'Hollander (UGent) , Jack Dongarra, Ian Foster, Lucio Grandinetti and Gerhard Joubert(2013) 24. -
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Performance modeling for FPGAs: extending the roofline model with high-level synthesis tools
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Study of combining GPU/FPGA accelerators for high-performance computing
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Performance and toolchain of a combined GPU/FPGA desktop
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GUDI: A combined GPU/FPGA Desktop System for Accelerating Image Processing Applications
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ParaFPGA 2011 : high performance computing with multiple FPGAs : design, methodology and applications
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- Book Editor
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Applications, tools and techniques on the road to exascale computing
Koen De Bosschere (UGent) , Erik D'Hollander (UGent) , Gerhard R Joubert, David Padua, Frans Peters and Mark Sawyer(2012) 22. -
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A combined GPGPU-FPGA high-performance desktop
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High-performance computing for low-power systems
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Parallel computing 2011, ParCo 2011: book of abstracts
(2011) -
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ParaFPGA : parallel computing with flexible hardware
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Refactoring for data locality
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High performance computing with FPGAs
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Efficient memory management for hardware accelerated Java Virtual Machines
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- Journal Article
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Refactoring intermediately executed code to reduce cache capacity misses
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Finding and applying loop transformations for generating optimized FPGA implementations
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Parallel computing with FPGAs: concepts and applications
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Intermediately Executed Code is the Key to Find Refactorings that Improve Temporal Data Locality
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Discovery of locality-improving refactorings by reuse path analysis
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RDVIS: a tool that visualizes the causes of low locality and hints program optimizations
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Making XML document markup international
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Generating cache hints for improved program efficiency
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Non-uniform dependences partitioned by recurrence chains
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Performance visualizations using XML representations
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Platform-independent cache optimization by pinpointing low-locality reuse
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- Journal Article
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Using hammock graphs to structure programs
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Software refactoring guided by multiple soft-goals
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Locality-Aware Code Generation using EPIC Extensions
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Reuse distance-based cache hint selection
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Compile-Time Cache Hint Generationfor EPIC Architectures
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Visualization enables the programmer to reduce cache misses
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Visualizing the impact of the cache on program execution