ereprof. dr. ir. Erik D'Hollander
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ParaFPGA15 : exploring threads and trends in programmable hardware
(2016) PARALLEL COMPUTING : ON THE ROAD TO EXASCALE. In Advances in Parallel Computing 27. p.501-504 -
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High-level synthesis optimization for blocked floating-point matrix multiplication
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High-level synthesis for FPGAs, the Swiss army knife for high-performance computing
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- Conference Paper
- C1
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Performance and resource modeling for FPGAs using high-level synthesis tools
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- Conference Paper
- P1
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ParaFPGA 2013 : harnessing programs, power and performance in parallel FPGA applications