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Expanded-beam through-substrate coupling interface for alignment tolerant packaging of silicon photonics
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Automatic architectural style detection using one-class support vector machines and graph kernels
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A graph-theoretic implementation of the Rabo-de-Bacalhau transformation grammar
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A semi-automatic approach for the definition of shape grammar rules
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Toward a visual approach in the exploration of shape grammars
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- Book
- open access
Hoger onderwijs voor de digitale eeuw
(2015) 34. -
- Conference Paper
- P1
- open access
Low-voltage Ge avalanche photodetector for highly sensitive 10Gb/s Si photonic receivers
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Design space exploration using a shape grammar implementation
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A generative approach towards performance-based design: using a shape grammar implementation
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- Journal Article
- A1
- open access
Design thinking support: information systems versus reasoning
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Towards a simulation of Peirce's cycle of abductive, deductive and inductive reasoning
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Optimization in compliance checking using heuristics: Flemish Energy Performance Regulations (EPR)
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- Conference Paper
- P1
- open access
Information system support in construction industry with semantic web technologies and/or autonomous reasoning agents
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Linking a game engine environment to architectural information on the semantic web
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- Conference Paper
- C1
- open access
A nice thing about standards
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Three-dimensional information exchange over the semantic web for the domain of architecture, engineering, and construction
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- Conference Paper
- C1
- open access
Increasing information feed in the process of structural steel design
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- Conference Paper
- C1
- open access
Extending the design process into the knowledge of the world
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A semantic rule checking environment for building performance checking
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- Conference Paper
- C1
- open access
Interoperability for the design and construction industry through semantic web technology
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- Conference Paper
- P1
- open access
Cycle-accurate evaluation of reconfigurable photonic networks-on-chip
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- Conference Paper
- C1
- open access
Visualisation of semantic architectural information within a game engine environment
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3D architectural design in the semantic web
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Accelerating event-driven simulation of spiking neurons with multiple synaptic time constants
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InP/InGaAs photodetector on SOI circuitry
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Pruning and regularization in reservoir computing
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- Conference Paper
- C1
- open access
Architectural study of reconfigurable photonic networks-on-chip for multi-core processors
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- Conference Paper
- C1
- open access
Low-power reconfigurable network architecture for on-chip photonic interconnects
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Semantics-based design: can ontologies help in a preliminary design phase?
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Using method interception for hardware/software co-development
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- Conference Paper
- C1
- open access
Architectural information modelling to address limitations of BIM in the design practice
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- Conference Paper
- C1
- open access
Architectural Information Modelling in Construction History
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- Conference Paper
- P1
- open access
IFC-based calculation of the Flemish Energy Performance Standard
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Constructing application-specific memory hierarchies on FPGAs
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Rent's rule and parallel programs: characterizing network traffic behavior
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Pruning and regularization in Reservoir Computing: a first insight
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Design of a reconfigurable optical interconnect for large-scale multiprocessor networks
(2008) PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE). 6996. p.69961H/1-69961H/10 -
- Conference Paper
- C1
- open access
Building an Application-specific Memory Hierarchy on FPGA
(2008) p.53-62 -
Runtime variability in scientific parallel applications
(2008) p.37-46 -
Photonic reservoir computing with coupled semiconductor optical amplifiers
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- Conference Paper
- C1
- open access
InGaAs/InP membrane photodetector bonded on silicon
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- Conference Paper
- C1
- open access
Indium phosphide based membrane photodetector for optical interconnects on silicon
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- Journal Article
- A1
- open access
Toward optical signal processing using photonic reservoir computing
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Industry Foundation Classes: a Space-Based Model Scheme?
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- Conference Paper
- C1
- open access
Architectural Information Modelling for Virtual Heritage Application
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Predicting the performance of reconfigurable optical interconnects in distributed shared-memory systems
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Synchronous parallel optical I/O on CMOS: A case study of the uniformity issue.
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Compact hardware liquid state machines on FPGA for real-time speech recognition
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- Conference Paper
- P1
- open access
Compact hardware for real-time speech recognition using a liquid state machine
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The introduction of time-scales in Reservoir Computing, applied to isolated digits recognition
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Linking non-binned spike train kernels to several existing spike train metrics
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Predicting reconfigurable interconnect performance in distributed shared-memory systems
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Finding and applying loop transformations for generating optimized FPGA implementations
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Generative modeling of autonomous robots and their environments using reservoir computing
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Energieprestatieberekening door middel van een Building Information Model.
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- Conference Paper
- C1
- open access
Finding Bounds on Ehrhart Quasi-Polynomials
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- Conference Paper
- C1
- open access
An overview of reservoir computing: theory, applications and implementations
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- Conference Paper
- P1
- open access
Synthetic traffic generation as a tool for dynamic interconnect evaluation
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- Conference Paper
- C1
- open access
Adapting reservoirs to get Gaussian distributions
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- Conference Paper
- C1
- open access
Performance Evaluation of Large Reconfigurable Interconnects for Multiprocessor Systems
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Silicon photonics
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- Conference Paper
- C1
- open access
Performance of large-scale reconfigurable optical interconnection networks in DSM systems
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- Conference Paper
- C1
- open access
Electrically pumped Inp-based microdisk lasers integrated with a nanophotonic SOI waveguide circuit
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- Conference Paper
- C1
- open access
III-V/silicon photonics for optical interconnects: bonding technology and integrated devices
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- Journal Article
- A1
- open access
Systematic simulation-based predictive synthesis of integrated optical interconnect
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- Conference Paper
- C1
- open access
A photonic interconnect layer on CMOS (invited paper)
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Silicon nanophotonics in CMOS
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- Conference Paper
- P1
- open access
Selective optical broadcasting in reconfigurable multiprocessor interconnects - art. no. 61850J
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InP on silicon electrically driven microdisk lasers for photonic ICs
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- Conference Paper
- P1
- open access
Reconfigurable interconnects in DSM systems: a focus on context switch behavior
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Backpropagation for population-temporal coded spiking neural networks
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- Conference Paper
- P1
- open access
Reconfigurable interconnection networks in Distributed Shared Memory systems: a study on communication patterns
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- Conference Paper
- P1
- open access
Speeding up multiprocessor machines with reconfigurable optical interconnects - art. no. 61240K
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- Miscellaneous
- open access
Hardware Generation from the Polyhedral Model
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- Conference Paper
- C1
- open access
Parallel Hardware Implementation of a Broad Class of Spiking Neurons using Serial Arithmetic
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- Miscellaneous
- open access
Predicting the Performance of Reconfigurable Interconnects in Distributed Shared-Memory Systems
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Predicting the Performance of Reconfigurable Interconnects in Shared-Memory Systems
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- Conference Paper
- C1
- open access
Linking Non-binned Spike Train Kernels to Several Existing Spike Train Metrics
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- Conference Paper
- C1
- open access
From Loop Transformation to Hardware Generation
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Reconfigurable Optical Networks for On-Chip Multiprocessors
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Loop transformations for generating scalable hardware
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Congestion Modeling for Reconfigurable Inter-Processor Networks
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Analysis of localized high-frequency substrate noise
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Selective optical broadcast component for reconfigurable multiprocessor, interconnects
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A simple on-chip repetitive sampling setup for the quantification of substrate noise
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Reconfigurable Optical Interconnects for Distributed Shared-Memory Multiprocessors
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Tuning the M-coder to improve Dirac`s Entropy Coding
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Reconfigurable Optical Interconnects for Distributed Shared-Memory Systems
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Isolated word recognition with the Liquid State Machine: a case study
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Predicting the Performance of Reconfigurable Interconnects in Distributed Shared-Memory Systems
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Wavelength Tuneable Reconfigurable Optical Interconnection Network for Shared-Memory Machines
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Speeding Up Dirac`s Entropy Codec
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Recognition of Isolated Digits using a Liquid State Machine
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Traffic Temporal Analysis for Reconfigurable Interconnects in Shared-Memory Systems
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Prediction Model for Evaluation of Reconfigurable Interconnects in Distributed Shared-Memory Systems
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Selective Broadcasting for Reconfigurable Optical Interconnects in DSM systems
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Photonic interconnects to silicon chips
(2004) PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE). 5359. p.337-351 -
A parallel optical interconnect link with on-chip optical access
(2004) PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE). 5453. p.124-133 -
Extending SpikeProp
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Improving SpikeProp: Enhancements to An Error-Backpropagation Rule for Spiking Neural Networks
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Traffic Locality Analysis for Reconfigurable Interconnects in Shared-Memory Systems
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Toward the accurate prediction of placement wire length distributions in VLSI circuits
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Plastic micro-optical modules for VCSEL based free-space intra-chip interconnections: demonstrator testbeds with OE-FPGA's
(2003) PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE). 4942. p.324-332 -
Reconfigurable optical interconnects for parallel computer systems : design space issues
(2003) PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE). 4942. p.236-246 -
- Conference Paper
- P1
- open access
A circuit-level simulation approach to analyse system level behaviour of VCSEL-based optical interconnects.
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- Conference Paper
- P1
- open access
An exploration of synchronization solutions for parallel short-range optical interconnect in mesochronous systems
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BSA, a fast and accurate spike train encoding scheme
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Low-loss, single-mode photonic wires and ring resonators in silicon-on-insulator
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Handcrafting Pulsed Neural Networks for the CAM-Brain Machine
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- Conference Paper
- C1
- open access
Design Methodology Development for VCSEL-based Guided-Wave Optical Interconnects
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A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits
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Low-cost microoptical modules for MCM level optical interconnections
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Demonstration of manufacturable free-space modules for multi-channel intra-chip optical interconnects
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Multi-channel free-space intra-chip optical interconnections: combining plastic micro-optical modules and VCSEL based OE-FPGA
(2002) PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE). 4652. p.177-185 -
Digital neural networks in the CAM-Brain Machine
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Multi-channel optical intra-chip interconnections based on free space modules: towards manufacturable solutions.
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Demonstrator Testbed for Intra-Chip Optical Interconnections: Combining Multi-Channel Free-Space Plastic Micro-Optical Modules and VCSEL Based OE-FPGAs.
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A Probabilistic Approach to Clock Cycle Prediction
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Getting more out of Donath`s hierarchical model for interconnect prediction
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AQUASUN: adaptive window query processing in CAD applications for physical design and verification
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Digital neural networks in the CAM-Brain Machine
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An XML-based framework for content adaption.
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Synthetic Benchmark Circuits for Timing-driven Physical Design Applications.
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Een computer met verstand
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A stochastic model for the interconnection topology of digital circuits
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Low-cost MOEM interconnect modules for Tb/s.cm(2) aggregate bandwidth to Silicon chips
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Demonstrating optoelectronic interconnect in a FPGA based prototype system using flip chip mounted 2D arrays of optical components and 2D POF-ribbon arrays as optical pathways
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Impact of optical I/O on FPGA electronic routing delays
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Demonstrating POF based optoelectronic interconnect in a multi-FPGA prototype system
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Sense and nonsense of logic-level optical interconnect: reflections on an experiment
(2001) PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE). 4455. p.151-159 -
Free-space micro-optical modules: the missing link for photonic interconnects to silicon chips.
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On Partitioning vs. Placement Rent Properties.
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On Rent's Rule for Rectangular Regions.
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Plastic micro-optical modules for high throughput inter-chip optical interconnections.
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Two dimensional optical interconnect between CMOS IC's
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On synthetic benchmark generation methods
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Design and realisation of high-speed transmitter arrays based on CMOS integrated drivers and resonant cavity LEDs
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Free-space micro-optical intra-MCM interconnection modules: performances, potentialities and limitations
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An optical area I/O enhanced FPGA with 256 optical channels per chip.
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Quantifying the Performance of Optoelectronic FPGA's: The Impact of Optical Interconnect Latency. Kluwer Academic Publishers, Boston, 2000, 195-202.
(2000) -
Computing Structures and optical interconnect: friends or foes?
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A Stochastic Model for Interconnection Complexity based on Rent's Rule.
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On Synthetic Benchmark Generation Methods.
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Architectural approach to the role of optics in monoprocessor and multiprocessor machines.
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Generating synthetic benchmark circuits for evaluating CAD tools.
(2000) IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 19(9). p.1011-1022 -
Technologies for two-dimensional optical interconnect between CMOS IC's
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Accurate interconnection length estimations for predictions early in the design cycle.
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Optoelectronic FPGA's.
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Generating new benchmark designs using a multi-terminal net model.
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A multi-FPGA demonstrator with POF-based optical area interconnect.
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On the Organization and Implementation of a Fixed-Length Block Structured Instruction Set Architecture.
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Investigating the Implementation of a Block Structured Processor Architecture in an Early Design Stage.
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Quantifying the impact of optical interconnect latency on the performance of optoelectronic FPGAs.
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Towards Synthetic Benchmark Circuits for Evaluating Timing-Driven CAD Tools.
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A fast, cache-aware algorithm for the calculation of radiological paths exploiting subword parallelism.
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Exploitable levels of ILP in future processors.
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A quantitative study of the benefits of area-I/O in FPGAs
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Optically interconnected integrated circuits to solve the CMOS interconnect bottleneck
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Latency requirements of optical interconnects at different memory hierarchy levels of a computer system
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Evaluation of FPGA Switch Matrices using a Monte Carlo Approach
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Aspects of a Fixed-Length Block Structured Instruction Set to Improve Loop Performance
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Improving Loop Performance on a Block Structured Architecture through Predication
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A Quantitative Study of Optical Interconnects at the L2-cache to Main Memory Level in a Uniprocessor
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Optical Interconnects at the L2 Cache to Main Memory Level in a Computer System and the Effect of Prefetching
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Latency Requirements of Optical Interconnects at Different Memory Hierarchy Levels of a Computer System
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ESCAPE: Environment for the Simulation of Computer Architectures for the Purpose of Education
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A Quantitative Study of The Benefits of Area-I/O in FPGAs
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On the use of subword parallelism in medical image processing.
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Optics and the CMOS interconnection problem: a systems and circuits perspective.
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An Analytical Model for Performance Estimation of Modern Data-Flow Style Scheduling Microprocessors
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Microarchitectural Issues of a Fixed Length Block Structured Instruction Set Architecture
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Issues in Compilation for Fixed-Length Block Structured Instruction Set Architectures
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Estimating Logic Cell to I/O Pad Lengths in Computer Systems
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Three-dimensional Optoelectronic Architectures for Massively Parallel Processing
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Optical interconnect solutions to the I/O-problem in future CMOS generations (invited paper)
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Estimating interconnection lengths in three-dimensional computer systems.
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A quantitative analysis of the benefits of the use of area-I/O pads in FPGAs.
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Micro-cavity LED's and their application in optical interconnect research within the IUAP-24 project (Invited Paper).
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A C++ Simulator modelling a modern data-flow scheduling Microprocessor
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Simulating a Modern Data-flow Scheduling Microprocessor in C++
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Micro-cavity LED's and their application in optical interconnect research within the IUAP-24 project (invited).
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Ultrasonic Perception: Tri-aural Sensor Array for Robots using a Competition Neural Network Approach
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PARALLEL COMPUTING: State-of-the-Art and Perspectives
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A Microarchitecture for a fixed length Block Structured instruction set Architecture
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Estimating Interconnection Lengths in Three-dimensional Computer Systems
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Hierarhical Test Generation with Built-in Fault Diagnosis
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An accurate interconnection length estimation for computer logic
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Ultrasonic Perception of Mobile Robots: A Comparison of Competition Neural Network and Feedforward Neural Network Techniques for Sensor Array Signal Processing
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Interconnection length distributions in 3-dimensional anisotropic systems
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Towards an Extension of Rent's Rule for Describing Local Variations in Interconnection Complexity
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Modeling signal distribution in optoelectronic architectures
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Arrays of light emitting diodes with integrated diffractive microlenses for board-to-board optical interconnect applications: design, modelling and experimental assessment.
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Optoelectronic Information Technology, Interuniversity Pole of Attraction 24
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Printnet: A Memory-Effcient Transparent Print-Facility for MS-DOS. International Journal of Mini & Microcomputers, Acta Press, Vol. 16, nr. 2, pp. 94-99
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A Optoelectronic 3-D Field Programmable Gate Arra. , Prague, 1994.
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IUAP-24 : Optoelectronic Information Technology
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Some Low-level Issues in the Implementation of a Shared Blackboard. Proc. Euromicro Workshop on Parallel and Distributed Processing, 27-29/1/1993, pp. 88-95, Gran Canaria, 1993.
(1993) -
A CORRELATION COPROCESSOR FOR ACCURATE REAL-TIME ULTRASONIC RANGING OF MULTIPLE OBJECTS USING THE TRANSPUTER.
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A Programming Environment for Sensor-Controlled Robots. NATO-ASI Series, 1991, Vol. F71, pp. 155-169.
(1991) -
Printnet: A Memory-Efficient Transparant Print-Facility for MS-DOS. Proc. of the 9th IASTED Intern. Symp. on Applied Informatics, 1991, pp. 96-99.
(1991) -
Time integration grey scales for ferroelectric LCD's
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Asynchronous parallel programming techniques for compliant robot motions
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Language coprocessor to support the interpretation of MODULA-2 programs
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Maximum entropy and conditional probability
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The arbitrary relation between probability of error and measurement subset
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Stochastic-model for closed-loop preemptive microprocessor I/O organizations
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On the peaking of the Hughes mean recognition accuracy : the resolution of an apparent paradox
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On the possible orderings in the measurement selection problem
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Method to eliminate drift effects in hall-mobility measurements
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Driedimensionale Opto-Elektronische Architecturen. Proceedings URSIForum 1994, pp. 67-70, 1994.
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Modeling and Evaluating Optoelectronic Architectures. SPIE International Symposium, SPIE, Vol. 2153, pp. 307-314, Los Angeles, 1994.
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VHDL-based Architectural Design of GRECO, a High-Performance Screening Coprocessor Fifth Eurochip workshop on VLSI Training, 17-19 October, CEC-DG III, pp. 139-144, Dresden, 1994.
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A transputer-Based Neural Network to Determine Object Positions from Tri-Aural Ultrasonic Sensor Data. Proc. of the Euromicro Workshop on Parallel and Distributed Computing, IEEE Comp. Soc. Press, p. 93-100, Malaga, 1994.
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Simulation of a Parallel Computer Graphics Architecture. Proc. of the 1994 European Simulation Symposium, Society for Computer Simulation. Vol. II, pp. 225-229, Istanbul, 1994.
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Parallel Raster Image Processor for PCB Manufacturing. Proc. of the IEEE IECON '94, 20th International Conference on Industrial Electronics, IES of IEEE, Vol. 2 of 3, pp. 1184-1189, Bologna, 1994.
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A Visual Real-Time Programming Language. Control Eng. Practice, Perga-mon Press, Vol. 1, Nr. 1, pp. 59-63, 1993.
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ASIC Support for the Real-time Accurate Ultrasonic Ranging of Multiple Objects using the Transputer. Proc. of the Eur. Conf. on Design Automation EDAC-EUROASIC, pp. 154-157, Parijs, 1993.
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Application of an Artificial Neural Network in an Object Localization System Using Ultrasonic Sensors. Proc. of the IASTED Int. Conf. on Robotics and Manufacturing, pp. 20-23, 1993.
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Tri-aural Perception on a Mobile Robot. IEEE Int. Conf. on Robotics and Automation, 2-6/5/1993, pp. 265-270, Atlanta, 1993.
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PRIP - A Parallel Raster Image Processor. Computer Graphics Forum, Vol. 12, pp. 95-104, 1993.
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Steps Towards Tri-Aural Perception. SPIE Conf. Proc.: Intelligent Robotic Systems: Sensor Fusion IV: Control Paradigms and Data Structures, 1991, Vol. 1611, pp. 165-176.
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The Evolution of the RISC Concept: A RISC Tutorial. BIRA Seminar, Antwerp, 1991, pp. 1-20.
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PRIP, A Parallel Raster Image Processor. Esprit Conference, 1991.