dr. ing. Ajeya Naithani
- ORCID iD
- 0000-0002-8291-4230
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Decoupled vector runahead
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Reliability-aware runahead
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- Journal Article
- A1
- open access
Vector runahead for indirect memory accesses
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- Journal Article
- A1
- open access
The forward slice core : a high-performance, yet low-complexity microarchitecture
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VMT : virtualized multi-threading for accelerating graph workloads on commodity processors
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Vector runahead
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- Conference Paper
- P1
- open access
The forward slice core microarchitecture
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- Conference Paper
- P1
- open access
Precise runahead execution
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- PhD Thesis
- open access
Improving soft error reliability in modern processors
(2019) -
- Journal Article
- A1
- open access
Precise runahead execution