dr. ing. Ajeya Naithani
- ORCID iD
-
0000-0002-8291-4230
Show
Sort by
-
- Conference Paper
- P1
- open access
Scalar Vector Runahead
-
- Journal Article
- A1
- open access
Decoupled vector runahead for prefetching nested memory-access chains
-
Decoupled vector runahead
-
Reliability-aware runahead
-
- Journal Article
- A1
- open access
Vector runahead for indirect memory accesses
-
- Journal Article
- A1
- open access
The forward slice core : a high-performance, yet low-complexity microarchitecture
-
VMT : virtualized multi-threading for accelerating graph workloads on commodity processors
-
Vector runahead
-
- Conference Paper
- P1
- open access
The forward slice core microarchitecture
-
- Conference Paper
- P1
- open access
Precise runahead execution