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SVtL: System Verification through Logic: tool support for verifying sliced hierarchical statecharts
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Protocol conformance through refinement mappings in Cadence SMV
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- Conference Paper
- C3
- open access
SVtL: System Verification through Logic: tool support for verifying sliced hierarchical statecharts
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- PhD Thesis
- open access
Towards the correctness of software behavior in UML : a model checking approach based on slicing
(2006) -
Protocol Conformance through Refinement Mappings in Cadence SMV
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- Conference Paper
- C3
- open access
UML-Based Approach to Developing Verified Embedded Software
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- Conference Paper
- C3
- open access
UML based Verification of Software
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- Conference Paper
- C3
- open access
Integrating Cadence SMV in the Verification of UML Software