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- Conference Paper
- P1
- open access
CRoute: a fast high-quality timing-driven connection-based FPGA router
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Hierarchical force-based block spreading for analytical FPGA placement
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How preserving circuit design hierarchy during FPGA packing leads to better performance
(2018) IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 37(3). p.629-642 -
Liquid : high quality scalable placement for large heterogeneous FPGAs
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Liquid : fast placement prototyping through steepest gradient descent movement
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- PhD Thesis
- open access
New FPGA design tools and architectures
(2016) -
Runtime-quality tradeoff in partitioning based multithreaded packing
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- Conference Paper
- P1
- open access
EXTRA : towards the exploitation of eXascale technology for reconfigurable architectures
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- Conference Paper
- P1
- open access
A fully parameterized virtual coarse grained reconfigurable array for high performance computing applications
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Logic Gates in the routing network of FPGAs (Abstract Only)
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- Conference Paper
- P1
- open access
EXTRA : towards an efficient open platform for reconfigurable high performance computing
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- Conference Paper
- P1
- open access
Estimating circuit delays in FPGAs after technology mapping
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- Conference Paper
- P1
- open access
Analyzing the divide between FPGA academic and commercial results
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- Journal Article
- A1
- open access
Identification of dynamic circuit specialization opportunities in RTL code
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FASTER: facilitating analysis and synthesis technologies for effective reconfiguration
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Parameterised FPGA reconfigurations for efficient test set generation
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TPaR: place and route tools for the dynamic reconfiguration of the FPGA's interconnect network
(2014) IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 33(3). p.370-383 -
Efficient implementation of virtual coarse grained reconfigurable arrays on FPGAs
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- Conference Paper
- C1
- open access
A novel tool flow for increased routing configuration similarity in multi-mode circuits
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- Conference Paper
- P1
- open access
A connection-based router for FPGAs
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Efficient implementation of virtual coarse grained reconfigurable arrays on FPGAS
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- Conference Paper
- C1
- open access
Maximizing the reuse of routing resources in a reconfiguration-aware connection router
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A connection router for the dynamic reconfiguration of FPGAs