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Analyzing the scalability of managed language applications with speedup stacks
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Improving IBM POWER8 performance through symbiotic job scheduling
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Mind the power holes : sifting operating points in power-limited heterogeneous multicores
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Analytical processor performance and power modeling using micro-architecture independent characteristics
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Symbiotic job scheduling on the IBM POWER8
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Micro-architecture independent analytical processor performance and power modeling
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Micro-architecture independent branch behavior modeling
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Revisiting symbiotic job scheduling
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- Journal Article
- A1
- open access
Mechanistic analytical modeling of superscalar in-order processor performance
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- Journal Article
- A1
- open access
Mechanistic modeling of architectural vulnerability factor
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The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism
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Multiprogram throughput metrics: a systematic approach
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An evaluation of high-level mechanistic core models
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Restating the case for weighted-IPC metrics to evaluate multiprogram workload performance
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Bottle graphs: visualizing scalability bottlenecks in multi-threaded applications
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Criticality stacks: identifying critical threads in parallel programs using synchronization behavior
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Per-thread cycle accounting in multicore processors
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An efficient CPI stack counter architecture for superscalar processors
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Probabilistic modeling for job symbiosis scheduling on SMT processors
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A first-order mechanistic model for architectural vulnerability factor
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- Conference Paper
- C1
- open access
A mechanistic performance model for superscalar in-order processors
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- Conference Paper
- C1
- open access
Speedup stacks: identifying scaling Bottlenecks in multi-threaded applications
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- Conference Paper
- C3
- open access
How sensitive is processor customization to the workload's input datasets?
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- Conference Paper
- C1
- open access
How sensitive is processor customization to the workload's input datasets?
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Fine-grained DVFS using on-chip regulators
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- Conference Paper
- C1
- open access
Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware
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A counter architecture for online DVFS profitability estimation
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Modeling critical sections in Amdahl's law and its implications for multicore design
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Probabilistic job symbiosis modeling for SMT processor scheduling
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Per-thread cycle accounting
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- Conference Paper
- P1
- open access
Interval simulation: raising the level of abstraction in architectural simulation
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Memory-level parallelism aware fetch policies for simultaneous multithreading processors
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A mechanistic performance model for superscalar out-of-order processors
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Per-thread cycle accounting in SMT processors
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MLP-Aware runahead threads in a simultaneous multithreading processor
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Raising the level of abstraction in architectural simulation
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Raising the level of abstraction in architectural simulation
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- PhD Thesis
- open access
Analytical performance analysis and modeling of superscalar and multi-threaded processors
(2008) -
Studying Compiler Optimizations on Superscalar Processors through Interval Analysis
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System-level performance metrics for multiprogram workloads
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A memory-level parallelism aware fetch policy for SMT processors
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A top-down approach to architecting CPI component performance counters
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Studying Compiler-Microarchitecture Interactions through Interval Analysis
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A performance counter architecture for computing accurate CPI components
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Efficient design space exploration of high performance embedded out-of-order processors
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Characterizing the branch misprediction penalty
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A performance counter architecture for computing accurate CPI components
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The shape of the processor design space and its implications for early stage explorations
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Accurately Warmed-up Trace Samples for the Evaluation of Cache Memories.