dr. ir. Karel Bruneel
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Automatically exploiting regularity in applications to reduce reconfiguration memory requirements
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- Conference Paper
- C1
- open access
Maximizing the reuse of routing resources in a reconfiguration-aware connection router
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- Conference Paper
- C1
- open access
Identifying opportunities for dynamic circuit specialization
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- Conference Paper
- P1
- open access
A dynamically reconfigurable pattern matcher for regular expressions on FPGA
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- Conference Paper
- C3
- open access
A human-friendly way of programming robots
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Mapping logic to reconfigurable FPGA routing
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A connection router for the dynamic reconfiguration of FPGAs
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- Conference Paper
- C1
- open access
Automating reconfiguration chain generation for SRL-based run-time reconfiguration
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- Journal Article
- A2
- open access
Dynamic circuit specialisation for key-based encryption algorithms and DNA alignment
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Dynamic data folding with parameterizable FPGA configurations
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- Conference Paper
- C1
- open access
Bouw een intelligente robot in de klas met Dwengo
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- Conference Paper
- C1
- open access
Robot competitions trick students into learning
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- Conference Paper
- C1
- open access
How parameterizable run-time FPGA reconfiguration can benefit adaptive embedded systems
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Efficiently generating FPGA configurations through a stack machine
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- Conference Paper
- C1
- open access
Memory-efficient and fast run-time reconfiguration of regularly structured designs